Logo

About

  • What is hdl-registers?
  • Release notes
  • New data file format in version 6.0.0
  • Contribution guide
  • License

User guide

  • Getting started
  • Working with data files
  • Working with Python API

Basic features

  • Register modes
  • Register arrays
  • Default registers

Register fields

  • Field overview
  • Bit fields
  • Bit vector fields
  • Enumeration fields
  • Integer fields

Register constants

  • Constant overview
  • Bit vector constants
  • Boolean constants
  • Float constants
  • Integer constants
  • String constants

Code generators

  • C generator
  • C++ generator
  • HTML generator
  • Python generator
  • SystemVerilog generator
  • VHDL generator

Extensions

  • Writing a custom code generator

API reference

  • hdl_registers package
  • hdl_registers.field package
  • hdl_registers.constant package
  • hdl_registers.generator package
  • hdl_registers.generator.c package
  • hdl_registers.generator.cpp package
  • hdl_registers.generator.html package
  • hdl_registers.generator.python package
  • hdl_registers.generator.systemverilog package
  • hdl_registers.generator.systemverilog.axi_lite package
  • hdl_registers.generator.vhdl package
  • hdl_registers.generator.vhdl.axi_lite package
  • hdl_registers.generator.vhdl.simulation package
  • hdl_registers.parser package
hdl-registers
  • Search

© Copyright Lukas Vik.

Built with Sphinx using a theme provided by Read the Docs.