hdl_registers.generator.vhdl.simulation package

Submodules

hdl_registers.generator.vhdl.simulation.check_package module

class hdl_registers.generator.vhdl.simulation.check_package.VhdlSimulationCheckPackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlSimulationGeneratorCommon

Generate VHDL code with simulation procedures to check the values of registers and fields. See the VHDL generator article for usage details.

  • For each readable register, procedures that check that the register’s current value is equal to a given expected value. Expected value can be provided as

    1. bit vector,

    2. integer, or

    3. native VHDL record type as given by VhdlRecordPackageGenerator.

  • For each field in each readable register, a procedure that checks that the register field’s current value is equal to a given natively-typed value.

Uses VUnit Verification Component calls, via the procedures from VhdlSimulationReadWritePackageGenerator.

The generated VHDL file needs also the generated packages from VhdlRegisterPackageGenerator and VhdlRecordPackageGenerator. See also Dependencies for further dependencies.

SHORT_DESCRIPTION = 'VHDL simulation check package'
create(**kwargs: Any) → Path

See super class for API details.

Overloaded here because this package file shall only be created if the register list actually has any registers.

get_code(**kwargs: Any) → str

Get a package with methods for checking register/field values.

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.simulation.read_write_package module

class hdl_registers.generator.vhdl.simulation.read_write_package.VhdlSimulationReadWritePackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlSimulationGeneratorCommon

Generate VHDL code with register read/write procedures that simplify simulation. See the VHDL generator article for usage details.

  • For each readable register, procedures that read the register value. Value can be read as:

    1. bit vector,

    2. integer, or

    3. native VHDL record type as given by VhdlRecordPackageGenerator.

  • For each field in each readable register, a procedure that reads the natively-typed value of the field.

  • For each writeable register, a procedure that writes the register value. Value can be written as:

    1. bit vector, or

    2. native VHDL record type as given by VhdlRecordPackageGenerator.

  • For each field in each writeable register, a procedure that writes a given natively-typed field value.

Uses VUnit Verification Component calls to create bus read/write operations.

The generated VHDL file needs also the generated packages from VhdlRegisterPackageGenerator and VhdlRecordPackageGenerator. See Dependencies for further dependencies.

SHORT_DESCRIPTION = 'VHDL simulation read/write package'
create(**kwargs: Any) → Path

See super class for API details.

Overloaded here because this package file shall only be created if the register list actually has any registers.

get_code(**kwargs: Any) → str

Get a package with methods for reading/writing registers.

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.simulation.vhdl_simulation_generator_common module

class hdl_registers.generator.vhdl.simulation.vhdl_simulation_generator_common.VhdlSimulationGeneratorCommon(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Common methods for generation of VHDL simulation code.

static get_array_index_association(register_array: RegisterArray | None) → str

Get the array index association. Suitable when associating the array index port to a read/write procedure call.

get_array_index_port(register_array: RegisterArray | None) → str

Get the array index port declaration. Suitable for VHDL procedure/function signatures that can read registers in arrays.

static get_base_address_message() → str

Status message for base address information. Suitable for error printouts.

Depends on a ‘base_address’ value being available as an ‘unsigned’ in VHDL.

static get_message() → str

Get the compounded status message. Suitable for error printouts.

Depends on a ‘base_message’ string being present in VHDL, as well as a ‘message’ string from user which might be empty.

static get_register_array_message(register_array: RegisterArray | None) → str

Status message for register array information. Suitable for error printouts.

If the register we are working on is in a register array, the ‘array_index’ value must be available as an integer in VHDL.

static reg_address_constant() → str

Get a ‘reg_address’ constant declaration, for the byte address of the current register. Depends on the ‘reg_index’ and ‘base_address’ constants being present in the VHDL.

Is suitable for implementation of register/field access procedures.

reg_index_constant(register: Register, register_array: RegisterArray | None = None) → str

Get a ‘reg_index’ constant declaration, for the index of the supplied register. If the register is in an array, the constant calculation depends on a ‘array_index’ being present in the VHDL.

Is suitable for implementation of register/field access procedures.

hdl_registers.generator.vhdl.simulation.wait_until_package module

class hdl_registers.generator.vhdl.simulation.wait_until_package.VhdlSimulationWaitUntilPackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlSimulationGeneratorCommon

Generate VHDL code with wait_until_X_equals procedures that simplify simulation. See the VHDL generator article for usage details.

  • For each readable register, a procedure that waits until the register assumes a given natively-typed record value.

  • For each field in each readable register, a procedure that waits until the field assumes a given natively-typed value.

Uses VUnit Verification Component calls to create bus read operations.

The generated VHDL file needs also the generated packages from VhdlRegisterPackageGenerator and VhdlRecordPackageGenerator. See Dependencies for further dependencies.

SHORT_DESCRIPTION = 'VHDL simulation wait until package'
create(**kwargs: Any) → Path

See super class for API details.

Overloaded here because this package file shall only be created if the register list actually has any registers.

get_code(**kwargs: Any) → str

Get a package with wait_until_X_equals methods for registers/fields.

property output_file: Path

Result will be placed in this file.