Register modes

Each register, whether plain or in a register array, must have a specified mode.

The different modes are defined by the class RegisterMode. In the documentation of that class you will find a diagram that explains the terms used when describing a mode.

The official register modes available in hdl-registers are defined by the REGISTER_MODES constant in register_modes. They are listed in the table below:

All available register modes.

Shorthand	Name	Description
r	Read	Software can read a value that hardware provides.
w	Write	Software can write a value that is available for hardware usage.
r_w	Read, Write	Software can write a value and read it back. The written value is available for hardware usage.
wpulse	Write-pulse	Software can write a value that is asserted for one clock cycle in hardware.
r_wpulse	Read, Write-pulse	Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware.

• The “Read”, “Write” and “Read, Write” modes are well-known and self-explanatory.

• The “Write-pulse” mode is a special mode suitable for “command”-style registers.

• The “Read, Write-pulse” mode is a special mode suitable for interrupt status registers, where a read shall show the current status and a write shall clear interrupts. Suitable for usage with interrupt_register.vhd.

Generated code

The chosen mode will highly affect the generated code.

For example a register of mode “Read” will only have getters in its generated C++ code, whereas mode “Write” will have only setters.

The generated VHDL package and AXI-Lite register file will implement the correct FPGA behavior for all the different modes. It will detect illegal operations and will e.g. respond with an RRESP of SLVERR if a read is attempted of a “Write” register.