Register modes
Each register, whether plain or in a register array, must have a specified mode.
The available register modes are listed in the table below.
Shorthand |
Name |
Description |
---|---|---|
r |
Read |
Bus can read a value that fabric provides. |
w |
Write |
Bus can write a value that is available for fabric usage. |
r_w |
Read, Write |
Bus can write a value and read it back. The written value is available for fabric usage. |
wpulse |
Write-pulse |
Bus can write a value that is asserted for one clock cycle in fabric. |
r_wpulse |
Read, Write-pulse |
Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
The “Read”, “Write” and “Read, Write” modes are well-known and self-explanatory.
The “Write-pulse” mode is a special mode suitable for “command”-style registers.
The “Read, Write-pulse” mode is a special mode suitable for interrupt status registers, where a read shall show the current status and a write shall clear interrupts. Suitable for usage with interrupt_register.vhd.
Generated code
The chosen mode will highly affect the generated code.
For example a register of mode “Read” will only have getters in its generated C++ code, whereas mode “Write” will have only setters.
The generated VHDL package used with axi_lite_reg_file.vhd will
implement the correct FPGA behavior for all the different modes.
It will detect illegal operations and will e.g. respond with an RRESP
of SLVERR
if a read
is attempted of a “Write” register.