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About

  • What is hdl-registers?
  • Release notes
  • New data file format in version 6.0.0
  • Contribution guide
  • License

User guide

  • Getting started
  • Working with data files
  • Working with Python API

Basic features

  • Register modes
  • Register arrays
  • Default registers

Register fields

  • Field overview
  • Bit fields
  • Bit vector fields
  • Enumeration fields
  • Integer fields

Register constants

  • Constant overview
  • Bit vector constants
  • Boolean constants
  • Float constants
  • Integer constants
  • String constants

Code generators

  • C generator
  • C++ generator
  • HTML generator
  • Python generator
  • SystemVerilog generator
  • VHDL generator

Extensions

  • Writing a custom code generator

API reference

  • hdl_registers package
    • Subpackages
      • hdl_registers.constant package
      • hdl_registers.field package
      • hdl_registers.generator package
        • Subpackages
        • Submodules
        • hdl_registers.generator.register_code_generator module
        • hdl_registers.generator.register_code_generator_helpers module
        • hdl_registers.generator.reserved_keywords module
      • hdl_registers.parser package
    • Submodules
    • hdl_registers.about module
    • hdl_registers.conftest module
    • hdl_registers.register module
    • hdl_registers.register_array module
    • hdl_registers.register_list module
    • hdl_registers.register_mode module
    • hdl_registers.register_modes module
  • hdl_registers.field package
  • hdl_registers.constant package
  • hdl_registers.generator package
    • Subpackages
      • hdl_registers.generator.c package
      • hdl_registers.generator.cpp package
      • hdl_registers.generator.html package
      • hdl_registers.generator.python package
      • hdl_registers.generator.systemverilog package
        • Subpackages
        • Submodules
        • hdl_registers.generator.systemverilog.reserved_keywords module
      • hdl_registers.generator.vhdl package
    • Submodules
    • hdl_registers.generator.register_code_generator module
    • hdl_registers.generator.register_code_generator_helpers module
    • hdl_registers.generator.reserved_keywords module
  • hdl_registers.generator.c package
  • hdl_registers.generator.cpp package
  • hdl_registers.generator.html package
  • hdl_registers.generator.python package
  • hdl_registers.generator.systemverilog package
    • Subpackages
      • hdl_registers.generator.systemverilog.axi_lite package
    • Submodules
    • hdl_registers.generator.systemverilog.reserved_keywords module
  • hdl_registers.generator.systemverilog.axi_lite package
  • hdl_registers.generator.vhdl package
  • hdl_registers.generator.vhdl.axi_lite package
  • hdl_registers.generator.vhdl.simulation package
  • hdl_registers.parser package
hdl-registers
  • hdl_registers package
  • hdl_registers.generator package
  • hdl_registers.generator.systemverilog package
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hdl_registers.generator.systemverilog package

Subpackages

  • hdl_registers.generator.systemverilog.axi_lite package
    • Submodules
    • hdl_registers.generator.systemverilog.axi_lite.register_file module
      • HdlRegistersImporter
        • HdlRegistersImporter.import_register_list()
      • SystemVerilogAxiLiteGenerator
        • SystemVerilogAxiLiteGenerator.COMMENT_START
        • SystemVerilogAxiLiteGenerator.SHORT_DESCRIPTION
        • SystemVerilogAxiLiteGenerator.get_code()
        • SystemVerilogAxiLiteGenerator.output_file
        • SystemVerilogAxiLiteGenerator.output_files
        • SystemVerilogAxiLiteGenerator.should_create
      • to_systemrdl()

Submodules

hdl_registers.generator.systemverilog.reserved_keywords module

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