hdl_registers.generator.vhdl.axi_lite package

Submodules

hdl_registers.generator.vhdl.axi_lite.wrapper module

class hdl_registers.generator.vhdl.axi_lite.wrapper.VhdlAxiLiteWrapperGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Generate a VHDL wrapper around a generic AXI-Lite register file with correct generics and ports. See the VHDL generator article for usage details.

The wrapper will set the correct generics and will use record types for regs_up and regs_down. This makes it very easy-to-use and saves a lot of manual conversion.

The file is dependent on the packages from VhdlRegisterPackageGenerator and VhdlRecordPackageGenerator. See also Dependencies for further dependencies.

Note that the regs_up port is only available if there are any registers of a type where hardware gives a value to the bus. For example a “Read” register. If instead, for example, there are only “Write” registers, the regs_up port will not be available and the type for it is not available in the VHDL package.

Same, but vice versa, for the regs_down port. Will only be available if there are any registers of a type where the bus provides a value to the hardware, e.g. “Read, Write”.

Similar concept for the reg_was_read and reg_was_written ports. They are only present if there are any readable/writeable registers in the register list.

SHORT_DESCRIPTION = 'VHDL AXI-Lite register file'

create(**kwargs: Any) → Path

See super class for API details.

Overloaded here because this file shall only be created if the register list actually has any registers.

get_code(**kwargs: Any) → str: Get VHDL code for a wrapper around the generic AXi_lite register file from hdl-modules:

property output_file: Path: Result will be placed in this file.