C code generator

A C header can be generated, that contains all information about registers, fields and constants. The code is generated from the CHeaderGenerator class by calling the RegisterCodeGenerator.create() method.

Python code that parses the example TOML file and generates the C code we need.
 1# Standard libraries
 2import sys
 3from pathlib import Path
 4
 5# First party libraries
 6from hdl_registers.generator.c.header import CHeaderGenerator
 7from hdl_registers.parser.toml import from_toml
 8
 9THIS_DIR = Path(__file__).parent
10
11
12def main(output_folder: Path):
13    """
14    Create register C artifacts from the TOML example file.
15    """
16    register_list = from_toml(
17        name="example",
18        toml_file=THIS_DIR.parent.parent / "user_guide" / "toml" / "toml_format.toml",
19    )
20
21    CHeaderGenerator(register_list=register_list, output_folder=output_folder).create()
22
23
24if __name__ == "__main__":
25    main(output_folder=Path(sys.argv[1]))

The C header provides two methods for usage: A struct that can be memory mapped, or address definitions that can be offset a base address. For the addresses, array registers use a macro with an array index argument.

Below is the resulting code from the TOML format example:

example_regs.h
 1// -----------------------------------------------------------------------------
 2// This file is automatically generated by hdl-registers version 7.0.2-dev.
 3// Code generator CHeaderGenerator version 1.0.0.
 4// Generated 2025-01-21 20:52 from file toml_format.toml at commit 3c3e6c67d817.
 5// Register hash 4df9765ebb584803b583628671e4659579eb85f4.
 6// -----------------------------------------------------------------------------
 7
 8#ifndef EXAMPLE_REGS_H
 9#define EXAMPLE_REGS_H
10
11// Value of register constant 'axi_data_width'.
12#define EXAMPLE_AXI_DATA_WIDTH (64)
13// Value of register constant 'clock_rate_hz'.
14#define EXAMPLE_CLOCK_RATE_HZ (156250000.0)
15
16// Number of registers within this register list.
17#define EXAMPLE_NUM_REGS (10u)
18
19// Type for the 'channels' register array.
20typedef struct example_channels_t
21{
22  // Mode 'Read, Write'.
23  uint32_t read_address;
24  // Mode 'Write'.
25  uint32_t config;
26} example_channels_t;
27
28// Type for this register list.
29typedef struct example_regs_t
30{
31  // Mode "Read, Write".
32  uint32_t config;
33  // Mode "Read".
34  uint32_t status;
35  example_channels_t channels[4];
36} example_regs_t;
37
38// Address of the 'config' register.
39// Mode 'Read, Write'.
40#define EXAMPLE_CONFIG_INDEX (0u)
41#define EXAMPLE_CONFIG_ADDR (4u * EXAMPLE_CONFIG_INDEX)
42// Attributes for the 'enable' field in the 'config' register.
43#define EXAMPLE_CONFIG_ENABLE_SHIFT (0u)
44#define EXAMPLE_CONFIG_ENABLE_MASK (0b1u << 0u)
45#define EXAMPLE_CONFIG_ENABLE_MASK_INVERSE (~EXAMPLE_CONFIG_ENABLE_MASK)
46// Attributes for the 'direction' field in the 'config' register.
47#define EXAMPLE_CONFIG_DIRECTION_SHIFT (1u)
48#define EXAMPLE_CONFIG_DIRECTION_MASK (0b11u << 1u)
49#define EXAMPLE_CONFIG_DIRECTION_MASK_INVERSE (~EXAMPLE_CONFIG_DIRECTION_MASK)
50enum ExampleConfigDirection
51{
52  EXAMPLE_CONFIG_DIRECTION_DATA_IN = 0,
53  EXAMPLE_CONFIG_DIRECTION_HIGH_Z = 1,
54  EXAMPLE_CONFIG_DIRECTION_DATA_OUT = 2,
55};
56
57// Address of the 'status' register.
58// Mode 'Read'.
59#define EXAMPLE_STATUS_INDEX (1u)
60#define EXAMPLE_STATUS_ADDR (4u * EXAMPLE_STATUS_INDEX)
61
62// Address of the 'read_address' register within the 'channels' register array (array_index < 4).
63// Mode 'Read, Write'.
64#define EXAMPLE_CHANNELS_READ_ADDRESS_INDEX(array_index) (2u + (array_index) * 2u + 0u)
65#define EXAMPLE_CHANNELS_READ_ADDRESS_ADDR(array_index) (4u * EXAMPLE_CHANNELS_READ_ADDRESS_INDEX(array_index))
66
67// Address of the 'config' register within the 'channels' register array (array_index < 4).
68// Mode 'Write'.
69#define EXAMPLE_CHANNELS_CONFIG_INDEX(array_index) (2u + (array_index) * 2u + 1u)
70#define EXAMPLE_CHANNELS_CONFIG_ADDR(array_index) (4u * EXAMPLE_CHANNELS_CONFIG_INDEX(array_index))
71// Attributes for the 'enable' field in the 'config' register within the 'channels' register array.
72#define EXAMPLE_CHANNELS_CONFIG_ENABLE_SHIFT (0u)
73#define EXAMPLE_CHANNELS_CONFIG_ENABLE_MASK (0b1u << 0u)
74#define EXAMPLE_CHANNELS_CONFIG_ENABLE_MASK_INVERSE (~EXAMPLE_CHANNELS_CONFIG_ENABLE_MASK)
75// Attributes for the 'tuser' field in the 'config' register within the 'channels' register array.
76#define EXAMPLE_CHANNELS_CONFIG_TUSER_SHIFT (1u)
77#define EXAMPLE_CHANNELS_CONFIG_TUSER_MASK (0b11111111u << 1u)
78#define EXAMPLE_CHANNELS_CONFIG_TUSER_MASK_INVERSE (~EXAMPLE_CHANNELS_CONFIG_TUSER_MASK)
79
80#endif // EXAMPLE_REGS_H