hdl_registers.generator.vhdl package

Subpackages

• hdl_registers.generator.vhdl.axi_lite package
  • Submodules
  • hdl_registers.generator.vhdl.axi_lite.wrapper module
    • VhdlAxiLiteWrapperGenerator
      • VhdlAxiLiteWrapperGenerator.SHORT_DESCRIPTION
      • VhdlAxiLiteWrapperGenerator.create()
      • VhdlAxiLiteWrapperGenerator.get_code()
      • VhdlAxiLiteWrapperGenerator.output_file
• hdl_registers.generator.vhdl.simulation package
  • Submodules
  • hdl_registers.generator.vhdl.simulation.check_package module
    • VhdlSimulationCheckPackageGenerator
      • VhdlSimulationCheckPackageGenerator.SHORT_DESCRIPTION
      • VhdlSimulationCheckPackageGenerator.create()
      • VhdlSimulationCheckPackageGenerator.get_code()
      • VhdlSimulationCheckPackageGenerator.output_file
  • hdl_registers.generator.vhdl.simulation.read_write_package module
    • VhdlSimulationReadWritePackageGenerator
      • VhdlSimulationReadWritePackageGenerator.SHORT_DESCRIPTION
      • VhdlSimulationReadWritePackageGenerator.create()
      • VhdlSimulationReadWritePackageGenerator.get_code()
      • VhdlSimulationReadWritePackageGenerator.output_file
  • hdl_registers.generator.vhdl.simulation.vhdl_simulation_generator_common module
    • VhdlSimulationGeneratorCommon
      • VhdlSimulationGeneratorCommon.get_array_index_association()
      • VhdlSimulationGeneratorCommon.get_array_index_port()
      • VhdlSimulationGeneratorCommon.get_base_address_message()
      • VhdlSimulationGeneratorCommon.get_message()
      • VhdlSimulationGeneratorCommon.get_register_array_message()
      • VhdlSimulationGeneratorCommon.reg_address_constant()
      • VhdlSimulationGeneratorCommon.reg_index_constant()
  • hdl_registers.generator.vhdl.simulation.wait_until_package module
    • VhdlSimulationWaitUntilPackageGenerator
      • VhdlSimulationWaitUntilPackageGenerator.SHORT_DESCRIPTION
      • VhdlSimulationWaitUntilPackageGenerator.create()
      • VhdlSimulationWaitUntilPackageGenerator.get_code()
      • VhdlSimulationWaitUntilPackageGenerator.output_file

Submodules

hdl_registers.generator.vhdl.record_package module

class hdl_registers.generator.vhdl.record_package.VhdlRecordPackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Generate a VHDL package with register record types containing natively-typed members for each register field. See the VHDL code generator article for usage details.

• For each register, plain or in array, a record with natively-typed members for each register field.

• For each register array, a correctly-ranged array of records for the registers in that array.

• Combined record with all the registers and register arrays. One each for registers in the up direction and in the down direction.

• Constants with default values for all of the above types.

• Conversion functions to/from std_logic_vector representation for all of the above types.

The generated VHDL file needs also the generated package from VhdlRegisterPackageGenerator.

SHORT_DESCRIPTION = 'VHDL record package'

create(**kwargs: Any) → Path

See super class for API details.

Overloaded here because this package file shall only be created if the register list actually has any registers.

get_code(**kwargs: Any) → str

Get a complete VHDL package with register record types.

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.register_package module

class hdl_registers.generator.vhdl.register_package.VhdlRegisterPackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Generate a base VHDL package with basic register information. See the VHDL code generator article for usage details.

• For each register constant, the value as a native VHDL constant.

• For each register, the index within the register map.

• For each field in each register

  • Register bit index range definitions.

  • Native VHDL type corresponding to the field type.

  • Conversion of a field value to/from SLV.

Also produces a register map constant, mapping indexes to modes, suitable for use with axi_lite_reg_file.vhd or VhdlAxiLiteWrapperGenerator.

SHORT_DESCRIPTION = 'VHDL register package'

get_code(**kwargs: Any) → str

Get a complete VHDL package with register and constant information.

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.reserved_keywords module

hdl_registers.generator.vhdl.vhdl_generator_common module

class hdl_registers.generator.vhdl.vhdl_generator_common.BusAccessDirection(read_or_write: str)

Bases: object

Keep track of and test the bus access direction.

__init__(read_or_write: str)

property name_adjective: str

Return “readable” or “writeable”.

register_is_accessible(register: Register) → bool

Return True if the supplied register is accessible in this direction.

class hdl_registers.generator.vhdl.vhdl_generator_common.FabricAccessDirection(up_or_down: str)

Bases: object

Keep track of and test the fabric access direction.

__init__(up_or_down: str)

register_is_accessible(register: Register) → bool

Return True if the supplied register is accessible in this direction.

class hdl_registers.generator.vhdl.vhdl_generator_common.VhdlGeneratorCommon(register_list: RegisterList, output_folder: Path)

Bases: RegisterCodeGenerator

Common methods for generation of VHDL code.

COMMENT_START: str = '--'

field_to_slv(field: RegisterField, field_name: str, value: str) → str

Get a VHDL snippet that converts a value of the given field to SLV. Via e.g. a function call or a cast.

Parameters:

• field – The field.

• field_name – The field’s qualified name.

• value – The name of the variable/constant that holds the field’s natively typed value.

static field_to_slv_function_name(field: RegisterField, field_name: str) → str

Name of the function that converts the field’s native VHDL representation to SLV.

Parameters:

• field – A field.

• field_name – The field’s qualified name.

field_type_name(register: Register, field: RegisterField, register_array: RegisterArray | None = None) → str

Get the native VHDL type name that will represent the value of the supplied field.

has_any_bus_accessible_register(direction: BusAccessDirection) → bool

Return True if the register list contains any register, plain or in array, that is bus-accessible in the given direction.

has_any_fabric_accessible_register(direction: FabricAccessDirection) → bool

Return True if the register list contains at least one register, plain or in array, with a mode where fabric accesses the value in the given direction.

iterate_bus_accessible_array_registers(register_array: RegisterArray, direction: BusAccessDirection) → Iterator[Register]

Iterate all registers in the register array that are bus-accessible in the given direction.

iterate_bus_accessible_plain_registers(direction: BusAccessDirection) → Iterator[Register]

Iterate all plain registers in the register list that are bus-accessible in the given direction.

iterate_bus_accessible_register_arrays(direction: BusAccessDirection) → Iterator[RegisterArray]

Iterate all register arrays in the register list that contain at least one register that is bus-accessible in the given direction.

iterate_bus_accessible_registers(direction: BusAccessDirection) → Iterator[tuple[Register, RegisterArray | None]]

Iterate all registers in the register list, plain or in array, that are bus-accessible in the given direction.

iterate_fabric_accessible_array_registers(register_array: RegisterArray, direction: FabricAccessDirection) → Iterator[Register]

Iterate all registers in the register array that are fabric-accessible in the given direction.

iterate_fabric_accessible_plain_registers(direction: FabricAccessDirection) → Iterator[Register]

Iterate all plain registers in the register list that are fabric-accessible in the given direction.

iterate_fabric_accessible_register_arrays(direction: FabricAccessDirection) → Iterator[RegisterArray]

Iterate all register arrays in the register list that contain at least one register that is fabric-accessible in the given direction.

iterate_fabric_accessible_registers(direction: FabricAccessDirection) → Iterator[tuple[Register, RegisterArray | None]]

Iterate all registers in the register list, plain or in array, that are fabric-accessible in the given direction.