hdl_registers.generator.vhdl package

Submodules

hdl_registers.generator.vhdl.axi_lite_wrapper module

class hdl_registers.generator.vhdl.axi_lite_wrapper.VhdlAxiLiteWrapperGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Generate a wrapper around generic AXI-Lite register files with correct generics and ports.

• https://hdl-modules.com/modules/reg_file/reg_file.html#axi-lite-reg-file-vhd

• https://github.com/hdl-modules/hdl-modules/blob/main/modules/reg_file/src/axi_lite_reg_file.vhd

The wrapper will set the correct generics and will use record types for regs_up and regs_down. This makes it very easy-to-use and saves a lot of manual conversion.

The generated VHDL file needs also the generated packages from VhdlRegisterPackageGenerator and VhdlRecordPackageGenerator.

Note that the regs_up port is only available if there are any registers of a type where fabric gives a value to the bus. For example a “Read” register. If instead, for example, there are only “Write” registers, the regs_up port will not be available and the type for it is not available in the VHDL package.

Same, but vice versa, for the regs_down port. Will only be available if there are any registers of a type where the bus provides a value to the fabric, e.g. “Read, Write”.

Similar concept for the reg_was_read and reg_was_written ports. They are only present if there are any readable/writeable registers in the register map.

SHORT_DESCRIPTION = 'VHDL AXI-Lite register file'

create(**kwargs: Any) → None

Overload the super method to implement our custom behavior.

get_code(**kwargs: Any) → str

Get VHDL code for a wrapper around the generic AXi_lite register file from hdl-modules:

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.record_package module

class hdl_registers.generator.vhdl.record_package.VhdlRecordPackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Generate a VHDL package with register record types containing natively-typed members for each register field.

• For each register, plain or in array, a record with natively-typed members for each register field.

• For each register array, a correctly-ranged array of records for the registers in that array.

• Combined record with all the registers and register arrays. One each for registers in the up direction and in the down direction.

• Constants with default values for all of the above types.

• Conversion functions to/from std_logic_vector representation for all of the above types.

The generated VHDL file needs also the generated package from VhdlRegisterPackageGenerator.

SHORT_DESCRIPTION = 'VHDL record package'

get_code(**kwargs: Any) → str

Get a complete VHDL package with register record types.

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.register_package module

class hdl_registers.generator.vhdl.register_package.VhdlRegisterPackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Generate a VHDL package with register information.

• For each register constant, the value as a native VHDL constant.

• For each register, the index within the register map.

• A register map constant, mapping indexes to modes.

• For each field in each register

  • Register bit index range definitions.

  • Native VHDL type corresponding to the field type.

  • Conversion of a field value to/from SLV.

SHORT_DESCRIPTION = 'VHDL register package'

get_code(**kwargs: Any) → str

Get a complete VHDL package with register and constant information.

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.simulation_package module

class hdl_registers.generator.vhdl.simulation_package.VhdlSimulationPackageGenerator(register_list: RegisterList, output_folder: Path)

Bases: VhdlGeneratorCommon

Generate code that simplifies simulation of a register map. Uses the VHDL record types for register read/write values.

• For each readable register

  • a procedure that reads the register and converts the value to the natively typed record.

  • a procedure that waits until the register assumes a given natively typed record value.

• For each field in each readable register

  • a procedure that reads the natively-typed value of the field.

  • a procedure that waits until the field assumes a given natively typed value.

• For each writeable register, a procedure that writes a given natively typed record value.

• For each field in each writeable register, a procedure that writes a given field value.

Uses VUnit Verification Component calls, via reg_operations_pkg.vhd from hdl_modules.

The generated VHDL file needs also the generated packages from VhdlRegisterPackageGenerator and VhdlRecordPackageGenerator.

SHORT_DESCRIPTION = 'VHDL simulation package'

get_code(**kwargs: Any) → str

Get a package with methods for reading/writing registers.

Parameters:

register_objects – Registers and register arrays to be included.

Returns:

VHDL code.

Return type:

str

property output_file: Path

Result will be placed in this file.

hdl_registers.generator.vhdl.vhdl_generator_common module

class hdl_registers.generator.vhdl.vhdl_generator_common.BusAccessDirection(read_or_write: str)

Bases: object

Keep track of and test the bus access direction.

__init__(read_or_write: str)

property name_adjective: str

Return “readable” or “writeable”.

register_is_accessible(register: Register) → bool

Return True if the supplied register is accessible in this direction.

class hdl_registers.generator.vhdl.vhdl_generator_common.FabricAccessDirection(up_or_down: str)

Bases: object

Keep track of and test the bus access direction.

__init__(up_or_down: str)

register_is_accessible(register: Register) → bool

Return True if the supplied register is accessible in this direction.

class hdl_registers.generator.vhdl.vhdl_generator_common.VhdlGeneratorCommon(register_list: RegisterList, output_folder: Path)

Bases: RegisterCodeGenerator, RegisterCodeGeneratorHelpers

Common methods for generation of VHDL code.

COMMENT_START: str = '--'

field_name(register: Register, field: RegisterField, register_array: RegisterArray | None = None) → str

Get the qualified field name, e.g. “<module name>_<register name>_<field_name>”. To be used where the scope requires it, i.e. outside of records.

field_to_slv(field: RegisterField, field_name: str, value: str) → str

Get a VHDL snippet that converts a value of the given field to SLV. Via e.g. a function call or a cast.

Parameters:

• field – A field.

• field_name – The field’s qualified name.

• value – The name of the variable/constant that holds the field’s natively typed value.

static field_to_slv_function_name(field: RegisterField, field_name: str) → str

Name of the function that converts the field’s native VHDL representation to SLV.

Parameters:

• field – A field.

• field_name – The field’s qualified name.

field_type_name(register: Register, field: RegisterField, register_array: RegisterArray | None = None) → str

Get the native VHDL type name that will represent the value of the supplied field.

has_any_bus_accessible_register(direction: BusAccessDirection) → bool

Return True if the register list contains any register, plain or in array, that is bus-accessible in the given direction.

has_any_fabric_accessible_register(direction: FabricAccessDirection) → bool

Return True if the register list contains at least one register, plain or in array, with a mode where fabric accesses the value in the given direction.

iterate_bus_accessible_array_registers(register_array: RegisterArray, direction: BusAccessDirection) → Iterator[Register]

Iterate all registers in the register array that are bus-accessible in the given direction.

iterate_bus_accessible_plain_registers(direction: BusAccessDirection) → Iterator[Register]

Iterate all plain registers in the register list that are bus-accessible in the given direction.

iterate_bus_accessible_register_arrays(direction: BusAccessDirection) → Iterator[RegisterArray]

Iterate all register arrays in the register list that contain at least one register that is bus-accessible in the given direction.

iterate_fabric_accessible_array_registers(register_array: RegisterArray, direction: FabricAccessDirection) → Iterator[Register]

Iterate all registers in the register array that are fabric-accessible in the given direction.

iterate_fabric_accessible_plain_registers(direction: FabricAccessDirection) → Iterator[Register]

Iterate all plain registers in the register list that are fabric-accessible in the given direction.

iterate_fabric_accessible_register_arrays(direction: FabricAccessDirection) → Iterator[RegisterArray]

Iterate all register arrays in the register list that contain at least one register that is fabric-accessible in the given direction.

iterate_fabric_accessible_registers(direction: FabricAccessDirection) → Iterator[tuple[Register, None | RegisterArray]]

Iterate all registers in the register list, plain or in array, that are fabric-accessible in the given direction.

register_array_name(register_array: RegisterArray) → str

Get the qualified register array name. To be used where the scope requires it, i.e. outside of records.

register_name(register: Register, register_array: RegisterArray | None = None) → str

Get the qualified register name, e.g. “<module name>_<register name>”. To be used where the scope requires it, i.e. outside of records.