hdl_registers.generator.systemverilog.axi_lite package
Submodules
hdl_registers.generator.systemverilog.axi_lite.register_file module
- class hdl_registers.generator.systemverilog.axi_lite.register_file.HdlRegistersImporter(compiler: RDLCompiler)
Bases:
RDLImporter
Importer class that translates the register data from hdl-registers representation to SystemRDL representation.
Warning
This is an internal class. Do not use it directly, API is subject to change.
- import_register_list(register_list: RegisterList) None
Call this method to perform the import.
- class hdl_registers.generator.systemverilog.axi_lite.register_file.SystemVerilogAxiLiteGenerator(register_list: RegisterList, output_folder: Path)
Bases:
RegisterCodeGenerator
Generate a SystemVerilog register file with AXI-Lite interface. See the SystemVerilog generator article for usage details.
This generator will create
the register file module, and
a package file.
The
RegisterCodeGenerator.create()
andRegisterCodeGenerator.create_if_needed()
methods in this generator can be supplied with aflatten_axi_lite
argument. See here for details.- SHORT_DESCRIPTION = 'SystemVerilog AXI-Lite register file'
- get_code(**kwargs: Any) str
Is required in the abstract base class, but not used in this generator. Do not call this method.
- property output_file: Path
Result will be placed in this file. This specific generator will also create a package file with the same name, but with a
_pkg
suffix.
- property output_files: Iterable[Path]
All the files that this generator creates.
- hdl_registers.generator.systemverilog.axi_lite.register_file.to_systemrdl(register_list: RegisterList) RootNode
Translate the register data from hdl-registers representation to SystemRDL representation.
Warning
This is an internal function. Do not use it directly, API is subject to change.