Release notes

Release history and changelog for the hdl-registers project. We follow the semantic versioning scheme MAJOR.MINOR.PATCH:

• MAJOR is bumped when incompatible API changes are made.

• MINOR is bumped when functionality is added in a backward-compatible manner.

• PATCH is bumped when backward-compatible bug fixes are made.

Unreleased (YYYY-MM-DD)

Changes since previous release

Nothing here yet.

8.1.0 (22 october 2025)

Changes since previous release

Added

• Add numerical interpretation for bit vector fields to data file parser (to support signed, unsigned fixed-point and signed fixed-point).

Fixes

• Add a few missing range checks in generated C++ code.

• Remove a few moot range checks in generated C++ code.

8.0.1 (17 may 2025)

Changes since previous release

Fixes

• Add missing reserved keyword check.

8.0.0 (29 april 2025)

Changes since previous release

Breaking changes

• Rework generated C++ API to use C++ struct with field values instead of raw uint32_t. See C++ generator for usage details.

  • get/set_<register> methods now return/take a struct with field values.

    • New alternative methods get/set_<register>_raw return/take a raw uint32_t register value instead of the casted structure.

  • get/set_<field> methods work just as before.

  • get_<field>_from_value methods are removed.

• Represent Bit field values as bool in generated C++ API.

• Represent BitVector field values with numerical interpretation Signed as int32_t in generated C++ API. Also UnsignedFixedPoint and SignedFixedPoint as float/double.

Breaking internal API changes

• Move Register properties utilized_width and default_value to RegisterCodeGeneratorHelpers.register_utilized_width() and RegisterCodeGeneratorHelpers.register_default_value_uint().

7.3.0 (1 april 2025)

Changes since previous release

Added

• Add support for specifying a numeric value as the default value for Bit vector fields.

• Add synchronous reset support to generated VHDL AXI-Lite register file.

Internal updates

• Simplify dependencies of generated VHDL code.

7.2.0 (14 march 2025)

Changes since previous release

Added

• Add SystemVerilog generator. The generator is in a beta state and is subject to API changes.

7.1.1 (11 march 2025)

Changes since previous release

Fixed

• Bump pegged tsfpga version.

7.1.0 (28 february 2025)

Changes since previous release

Added

• Add full RST and LaTeX math support in HTML generator by using docutils renderer.

Fixes

• Fix compiler warning due to redundant assertion in C++ code.

7.0.4 (19 february 2025)

Changes since previous release

Fixes

• Print only file name (not full path) in C++ assertion macros.

7.0.3 (11 february 2025)

Changes since previous release

Fixes

• Performance improvements, typing fixes, and internal refactoring as suggested by ruff linter.

7.0.2 (28 january 2025)

Changes since previous release

Fixed

• Fix bug in VHDL register package generator where some float constants would yield a compilation error related to E notation.

7.0.1 (18 january 2025)

Changes since previous release

Fixed

• Remove old VhdlAxiLiteWrapperGenerator artifacts from file system if they exist, to avoid confusion and compilation errors.

7.0.0 (18 january 2025)

Changes since previous release

Added

• Add custom assertion macro call for C++ runtime checks. Adds the possibility of user-defined handling of errors. See Assertion macros.

• Add Register.utilized_width property.

Breaking changes

• Generated VHDL code now requires hdl-modules version 6.0.0 or greater.

• The user must now implement an assertion_handler function and pass it as a constructor argument to the generated C++ class. See Assertion macros.

• Change type of C++ constructor base_address argument to be uintptr_t.

• Rename VhdlAxiLiteWrapperGenerator output file and entity name from <name>_reg_file to <name>_register_file_axi_lite.

Changes

• Significant resource optimizations of generated VHDL code.

• The RegisterCodeGenerator.create() method now includes the header lines in the generated code on its own. No need to call RegisterCodeGenerator.header() in RegisterCodeGenerator.get_code() in custom generators anymore.

6.2.0 (5 december 2024)

Changes since previous release

Added

• Add runtime check that provided C++ bit field setter value is in range.

Fixes

• Fix error when converting small negative values (sfixed) to binary in numerical_interpretation.to_unsigned_binary().

6.1.0 (13 november 2024)

Changes since previous release

Added

• Add simulation read/write functions for register values as integer and register_t to VhdlSimulationReadWritePackageGenerator.

• Add simulation check functions for register values as integer, register_t and native VHDL record to VhdlSimulationCheckPackageGenerator.

6.0.1 (27 august 2024)

Changes since previous release

Fixes

• Fix PyPI release version requirement conflict related to tsfpga.

6.0.0 (25 august 2024)

Changes since previous release

Breaking changes

• Update data file (TOML, JSON, etc) format in a way that is not compatible with old files. See New data file format in version 6.0.0. Note that old files are automatically updated. This change enables:

  • Fully user-configurable ordering and grouping of registers and register arrays.

  • Fully user-configurable ordering and grouping of fields in a register.

• Rename RegisterList.get_register() argument name to register_name.

Breaking internal API changes

• Remove RegisterField attributes range_str and default_value_str. This information is now calculated internally in the HTML generator class.

• Rename Enumeration.set_default_value() argument value to the more correct name.

• Rework register mode handling to use objects with properties instead of magic strings.

  • Change Register.__init__(), RegisterList.append_register(), and RegisterArray.append_register() arguments mode to be of type RegisterMode instead of str.

  • Move RegisterMode to register_mode and REGISTER_MODES to register_modes.

  • Rename RegisterMode property mode_readable to name.

  • Remove Register properties is_bus_readable and is_bus_writeable in favor of Register.mode.

  • Use Register.mode instead of generator-specific properties/checkers in VhdlGeneratorCommon.

• Rework the system for numerical interpretation of bit vector field values.

  • Remove field_type member from Bit, Enumeration, and Integer.

  • Rename FieldType class to NumericalInterpretation.

  • Rename field_type member of BitVector to BitVector.numerical_interpretation.

  • Rename field_type argument of BitVector.__init__() and Register.append_bit_vector() to numerical_interpretation.

  • Remove min_value and max_value properties from BitVector. Use BitVector.numerical_interpretation instead.

  • Remove bit_width argument from NumericalInterpretation.min_value(), NumericalInterpretation.max_value, NumericalInterpretation.convert_from_unsigned_binary(), and NumericalInterpretation.convert_to_unsigned_binary(). Add bit_width argument to Unsigned.__init__() and Signed.__init__().

  • Remove is_signed and max_binary_value properties of RegisterField. is_signed is still present for Integer. Bit vectors should use BitVector.numerical_interpretation.

5.2.0 (7 may 2024)

Changes since previous release

Added

• Add Python generator to read/write/print register and field values on a target device. See usage instructions here.

Requires tsfpga version 12.3.2 or later.

5.1.3 (3 april 2024)

Changes since previous release

Fixes

• Peg rtoml dependency package to 0.9.X so that pip install works on 64-bit Windows.

5.1.2 (11 march 2024)

Changes since previous release

Fixes

• Use consistent number formatting of fixed-point field values in VhdlSimulationCheckPackageGenerator error messages.

5.1.1 (8 march 2024)

Changes since previous release

Changes

• Improve timeout error message from VhdlSimulationWaitUntilPackageGenerator.

• Print relative file path when generating artifacts.

Requires tsfpga version 12.3.1 or later.

5.1.0 (5 february 2024)

Changes since previous release

Added

• Add generation of simulation support package that checks field values to VhdlSimulationCheckPackageGenerator.

  • Uses VUnit Verification Components for bus operations.

  • Generates a check_equal procedure for each field in each readable register.

  • Use native VHDL type for value representation.

5.0.0 (25 january 2024)

Changes since previous release

Fixes

• Fix bug where RegisterField.get_value() and RegisterField.set_value() would crash for negative-range integer fields.

• Fix “multiple definition” bug in generated C header for a string constant.

• Fix C++ field setters on registers of mode w, wpulse and r_wpulse not taking into account non-zero default values of other fields.

• Decrease RegisterList.object_hash() calculation time by 40%. Improves performance of RegisterCodeGenerator.should_create().

• Improve TOML parsing performance by a factor of ~8 by switching to rtoml instead of tomli package.

Added

• Add support for parsing JSON and YAML data files, see here.

• Add generation of register records with natively-typed members for each register field to VhdlRecordPackageGenerator.

• Add generation of simulation support package to VhdlSimulationReadWritePackageGenerator.

  • Uses VUnit Verification Components for bus operations.

  • Uses the natively typed records from VhdlRecordPackageGenerator for values.

  • Generates the following procedures:

    • Read/write for each register.

    • Read/write for each field.

• Add generation of simulation support package to VhdlSimulationWaitUntilPackageGenerator.

  • Uses VUnit Verification Components for bus operations.

  • Uses the natively typed records from VhdlRecordPackageGenerator for values.

  • Generates the following procedures:

    • Wait until register equals for each register.

    • Wait until field equals for each register.

• Add generation of a wrapper around axi_lite_register_file.vhd to VhdlAxiLiteWrapperGenerator.

  • Sets correct generics and uses the natively typed records from VhdlRecordPackageGenerator for its up/down register values.

• Add checks to Integer.get_value() and Integer.set_value() that values are within the configured range of the field.

Breaking changes

• Move RegisterParser to sub-package hdl_registers.parser. Break out from_toml() to separate Python module hdl_registers.parser.toml.

• Rename module_name argument of RegisterParser and from_toml() to name.

• Rename VHDL field conversion function for enumerations from to_<field name>_slv to to_slv.

• Remove C++ interface header constant <register array name>_array_length. Information is instead available as an attribute fpga_regs::<module name>::<register array name>::array_length.

• Rework code generator API for better performance and scalability.

  • Remove public members copy_source_definition, generated_info, generated_source_info from RegisterList.

  • Remove create_vhdl_package method from RegisterList. Move hdl_registers.register_vhdl_generator.RegisterVhdlGenerator class to VhdlRegisterPackageGenerator and update API. See VHDL generator for usage details.

  • Remove create_c_header method from RegisterList. Move hdl_registers.register_c_generator.RegisterCGenerator class to CHeaderGenerator and update API. See C generator for usage details.

  • Remove create_cpp_interface, create_cpp_header and create_cpp_implementation methods from RegisterList. Move hdl_registers.register_cpp_generator.RegisterCppGenerator class to CppInterfaceGenerator, CppHeaderGenerator, and CppImplementationGenerator, and update API. See C++ generator for usage details.

  • Remove create_html_page, create_html_register_table and create_html_constant_table methods from RegisterList. Move hdl_registers.register_html_generator.RegisterHtmlGenerator class to HtmlPageGenerator, HtmlRegisterTableGenerator, and HtmlConstantTableGenerator, and update API. See HTML generator for usage details.

  • Remove create_python_class method from RegisterList. Move hdl_registers.register_python_generator.RegisterPythonGenerator class to PythonPickleGenerator and update API. See Python generator for usage details.

4.1.0 (2 november 2023)

Changes since previous release

Added

• Add support for negative-range integer fields.

4.0.2 (18 october 2023)

Changes since previous release

Fix required Python version in PyPI package.

4.0.1 (11 october 2023)

Changes since previous release

Fix PyPI link to release notes.

4.0.0 (11 october 2023)

Changes since previous release

Fixes

• Use double data type for generated C/C++ header floating-point constants. Matches the precision in the generated VHDL code.

Breaking changes

• Break up hdl_registers.Constant class into BooleanConstant, FloatConstant, IntegerConstant and StringConstant that are placed in new constant sub-package.

• Move BitVector, Bit and RegisterField classes and register_field_type module from top-level to field sub-package.

• Move HtmlTranslator, RegisterCGenerator, RegisterCodeGenerator, RegisterCppGenerator, RegisterHtmlGenerator, RegisterPythonGenerator and RegisterVhdlGenerator classes from top-level to generator sub-package.

• Rename RegisterField.range to RegisterField.range_str().

• Remove default value description=None for argument to RegisterList.add_constant().

• Remove public method vhdl_typedef from FieldType class. This logic is instead moved to RegisterVhdlGenerator.

• Remove the largely unused “Value (hexadecimal)” constant information column from HTML generator.

• Remove textual descriptions of registers/arrays/fields/constants from generated C header.

Added

• Add support for unsigned bit vector constants via the UnsignedVectorConstant class.

• Add support for ranged integer register fields via the Integer class.

• Add support for enumeration register fields via the Enumeration class.

3.1.0 (25 april 2023)

Changes since previous release

Added

• Add support for register constants of type string.

3.0.2 (4 march 2023)

Changes since previous release

Added

• Add more comments to generated VHDL.

3.0.1 (3 march 2023)

Changes since previous release

• Update project slogan on PyPI to fit within 98 characters.

3.0.0 (3 march 2023)

Changes since previous release

Added

• Add field setters and getters to RegisterCppGenerator.

• Add *_MASK_INVERSE defines for fields to RegisterCGenerator.

• Add support for register constants of boolean and floating point type.

Breaking changes

• Remove the field _mask and _shift public constants from the generated C++ interface header. These are not needed now that setters and getters are available.

• Change to use unresolved VHDL types in RegisterVhdlGenerator class.

  • std_ulogic_vector instead of std_logic_vector.

  • u_signed instead of signed.

  • u_unsigned instead of unsigned.

Changes

• Increase TOML parsing performance by using tomli Python package instead of tomlkit.

2.1.0 (1 april 2022)

Changes since previous release

Added

• Add .RegisterList.create_python_class method to create a Python pickle file. Read more here.

• Add optional field_type argument to RegisterList.append_register() and Register.

• Add support for generating ieee.fixed_pkg types in RegisterVhdlGenerator class based on the register field_type.

Fixed

• Fix bug where setting default value for bit 31 in a register could fail.

2.0.1 (22 october 2021)

Changes since previous release

Second release to test PyPI deploy. Functionality is identical to tsfpga version 9.0.0.

2.0.0 (22 october 2021)

Initial release to test PyPI deploy. Functionality is identical to tsfpga version 9.0.0.