Release notes

Add generation of simulation support package that checks field values to VhdlSimulationCheckPackageGenerator.
- Uses VUnit Verification Components for bus operations.
- Generates a check_equal procedure for each field in each readable register.
- Use native VHDL type for value representation.

5.0.0 (25 january 2024)

Changes since previous release

Fixes

Fix bug where RegisterField.get_value() and RegisterField.set_value() would crash for negative-range integer fields.
Fix “multiple definition” bug in generated C header for a string constant.
Fix C++ field setters on registers of mode w, wpulse and r_wpulse not taking into account non-zero default values of other fields.
Decrease RegisterList.object_hash() calculation time by 40%. Improves performance of RegisterCodeGenerator.should_create().
Improve TOML parsing performance by a factor of ~8 by switching to rtoml instead of tomli package.

Added

Add support for parsing JSON and YAML data files, see here.
Add generation of register records with natively-typed members for each register field to VhdlRecordPackageGenerator.
Add generation of simulation support package to VhdlSimulationReadWritePackageGenerator.
- Uses VUnit Verification Components for bus operations.
- Uses the natively typed records from VhdlRecordPackageGenerator for values.
- Generates the following procedures:
  - Read/write for each register.
  - Read/write for each field.
Add generation of simulation support package to VhdlSimulationWaitUntilPackageGenerator.
- Uses VUnit Verification Components for bus operations.
- Uses the natively typed records from VhdlRecordPackageGenerator for values.
- Generates the following procedures:
  - Wait until register equals for each register.
  - Wait until field equals for each register.
Add generation of a wrapper around axi_lite_reg_file.vhd to VhdlAxiLiteWrapperGenerator.
- Sets correct generics and uses the natively typed records from VhdlRecordPackageGenerator for its up/down register values.
Add checks to Integer.get_value() and Integer.set_value() that values are within the configured range of the field.

Breaking changes

Move RegisterParser to sub-package hdl_registers.parser. Break out from_toml() to separate Python module hdl_registers.parser.toml.
Rename module_name argument of RegisterParser and from_toml() to name.
Rename VHDL field conversion function for enumerations from to_<field name>_slv to to_slv.
Remove C++ interface header constant <register array name>_array_length. Information is instead available as an attribute fpga_regs::<module name>::<register array name>::array_length.
Rework code generator API for better performance and scalability.
- Remove public members copy_source_definition, generated_info, generated_source_info from RegisterList.
- Remove create_vhdl_package method from RegisterList. Move hdl_registers.register_vhdl_generator.RegisterVhdlGenerator class to VhdlRegisterPackageGenerator and update API. See VHDL code generator for usage details.
- Remove create_c_header method from RegisterList. Move hdl_registers.register_c_generator.RegisterCGenerator class to CHeaderGenerator and update API. See C code generator for usage details.
- Remove create_cpp_interface, create_cpp_header and create_cpp_implementation methods from RegisterList. Move hdl_registers.register_cpp_generator.RegisterCppGenerator class to CppInterfaceGenerator, CppHeaderGenerator, and CppImplementationGenerator, and update API. See C++ code generator for usage details.
- Remove create_html_page, create_html_register_table and create_html_constant_table methods from RegisterList. Move hdl_registers.register_html_generator.RegisterHtmlGenerator class to HtmlPageGenerator, HtmlRegisterTableGenerator, and HtmlConstantTableGenerator, and update API. See HTML code generator for usage details.
- Remove create_python_class method from RegisterList. Move hdl_registers.register_python_generator.RegisterPythonGenerator class to PythonPickleGenerator and update API. See Python code generator for usage details.

4.1.0 (2 november 2023)

Changes since previous release

Added

Add support for negative-range integer fields.

4.0.2 (18 october 2023)

Changes since previous release

Fix required Python version in PyPI package.

4.0.1 (11 october 2023)

Changes since previous release

Fix PyPI link to release notes.

4.0.0 (11 october 2023)

Changes since previous release

Fixes

Use double data type for generated C/C++ header floating-point constants. Matches the precision in the generated VHDL code.

Breaking changes

Break up hdl_registers.Constant class into BooleanConstant, FloatConstant, IntegerConstant and StringConstant that are placed in new constant sub-package.
Move BitVector, Bit and RegisterField classes and register_field_type module from top-level to field sub-package.
Move HtmlTranslator, RegisterCGenerator, RegisterCodeGenerator, RegisterCppGenerator, RegisterHtmlGenerator, RegisterPythonGenerator and RegisterVhdlGenerator classes from top-level to generator sub-package.
Rename RegisterField.range to RegisterField.range_str().
Remove default value description=None for argument to RegisterList.add_constant().
Remove public method vhdl_typedef from FieldType class. This logic is instead moved to RegisterVhdlGenerator.
Remove the largely unused “Value (hexadecimal)” constant information column from HTML generator.
Remove textual descriptions of registers/arrays/fields/constants from generated C header.

Added

Add support for unsigned bit vector constants via the UnsignedVectorConstant class.
Add support for ranged integer register fields via the Integer class.
Add support for enumeration register fields via the Enumeration class.

3.1.0 (25 april 2023)

Changes since previous release

Added

Add support for register constants of type string.

3.0.2 (4 march 2023)

Changes since previous release

Added

Add more comments to generated VHDL.

3.0.1 (3 march 2023)

Changes since previous release

Update project slogan on PyPI to fit within 98 characters.

3.0.0 (3 march 2023)

Changes since previous release

Added

Add field setters and getters to RegisterCppGenerator.
Add *_MASK_INVERSE defines for fields to RegisterCGenerator.
Add support for register constants of boolean and floating point type.

Breaking changes

Remove the field _mask and _shift public constants from the generated C++ interface header. These are not needed now that setters and getters are available.
Change to use unresolved VHDL types in RegisterVhdlGenerator class.
- std_ulogic_vector instead of std_logic_vector.
- u_signed instead of signed.
- u_unsigned instead of unsigned.

Changes

Increase TOML parsing performance by using tomli Python package instead of tomlkit.

2.1.0 (1 april 2022)

Changes since previous release

Added

Add .RegisterList.create_python_class method to create a Python pickle file. Read more here.
Add optional field_type argument to RegisterList.append_register() and Register.
Add support for generating ieee.fixed_pkg types in RegisterVhdlGenerator class based on the register field_type.

Fixed

Fix bug where setting default value for bit 31 in a register could fail.

2.0.1 (22 october 2021)

Changes since previous release

Second release to test PyPI deploy. Functionality is identical to tsfpga version 9.0.0.

2.0.0 (22 october 2021)

Initial release to test PyPI deploy. Functionality is identical to tsfpga version 9.0.0.