Release notes
Release history and changelog for the hdl-registers project.
We follow the semantic versioning scheme MAJOR.MINOR.PATCH
:
MAJOR
is bumped when incompatible API changes are made.MINOR
is bumped when functionality is added in a backward-compatible manner.PATCH
is bumped when backward-compatible bug fixes are made.
Unreleased (YYYY-MM-DD)
Changes since previous release
Added
Add runtime check that provided C++ bit field setter value is in range.
6.1.0 (13 november 2024)
Changes since previous release
Added
Add simulation read/write functions for register values as
integer
andreg_t
toVhdlSimulationReadWritePackageGenerator
.Add simulation check functions for register values as
integer
,reg_t
and native VHDL record toVhdlSimulationCheckPackageGenerator
.
6.0.1 (27 august 2024)
Changes since previous release
Fixes
Fix PyPI release version requirement conflict related to tsfpga.
6.0.0 (25 august 2024)
Changes since previous release
Breaking changes
Update data file (TOML, JSON, etc) format in a way that is not compatible with old files. See New data file format in version 6.0.0. Note that old files are automatically updated. This change enables:
Fully user-configurable ordering and grouping of registers and register arrays.
Fully user-configurable ordering and grouping of fields in a register.
Rename
RegisterList.get_register()
argumentname
toregister_name
.
Breaking internal API changes
Remove
RegisterField
attributesrange_str
anddefault_value_str
. This information is now calculated internally in the HTML generator class.Rename
Enumeration.set_default_value()
argumentvalue
to the more correctname
.Rework register mode handling to use objects with properties instead of magic strings.
Change
Register.__init__()
,RegisterList.append_register()
, andRegisterArray.append_register()
argumentsmode
to be of typeRegisterMode
instead ofstr
.Move
RegisterMode
toregister_mode
andREGISTER_MODES
toregister_modes
.Rename
RegisterMode
propertymode_readable
toname
.Remove
Register
propertiesis_bus_readable
andis_bus_writeable
in favor ofRegister.mode
.Use
Register.mode
instead of generator-specific properties/checkers inVhdlGeneratorCommon
.
Rework the system for numerical interpretation of bit vector field values.
Remove
field_type
member fromBit
,Enumeration
, andInteger
.Rename
FieldType
class toNumericalInterpretation
.Rename
field_type
member ofBitVector
toBitVector.numerical_interpretation
.Rename
field_type
argument ofBitVector.__init__()
andRegister.append_bit_vector()
tonumerical_interpretation
.Remove
min_value
andmax_value
properties fromBitVector
. UseBitVector.numerical_interpretation
instead.Remove
bit_width
argument fromNumericalInterpretation.min_value()
,NumericalInterpretation.max_value
,NumericalInterpretation.convert_from_unsigned_binary()
, andNumericalInterpretation.convert_to_unsigned_binary()
. Addbit_width
argument toUnsigned.__init__()
andSigned.__init__()
.Remove
is_signed
andmax_binary_value
properties ofRegisterField
.is_signed
is still present forInteger
. Bit vectors should useBitVector.numerical_interpretation
.
5.2.0 (7 may 2024)
Changes since previous release
Added
Add Python generator to read/write/print register and field values on a target device. See usage instructions here.
Requires tsfpga version 12.3.2 or later.
5.1.3 (3 april 2024)
Changes since previous release
Fixes
Peg
rtoml
dependency package to 0.9.X so that pip install works on 64-bit Windows.
5.1.2 (11 march 2024)
Changes since previous release
Fixes
Use consistent number formatting of fixed-point field values in
VhdlSimulationCheckPackageGenerator
error messages.
5.1.1 (8 march 2024)
Changes since previous release
Changes
Improve timeout error message from
VhdlSimulationWaitUntilPackageGenerator
.Print relative file path when generating artifacts.
Requires tsfpga version 12.3.1 or later.
5.1.0 (5 february 2024)
Changes since previous release
Added
Add generation of simulation support package that checks field values to
VhdlSimulationCheckPackageGenerator
.Uses VUnit Verification Components for bus operations.
Generates a
check_equal
procedure for each field in each readable register.Use native VHDL type for value representation.
5.0.0 (25 january 2024)
Changes since previous release
Fixes
Fix bug where
RegisterField.get_value()
andRegisterField.set_value()
would crash for negative-range integer fields.Fix “multiple definition” bug in generated C header for a string constant.
Fix C++ field setters on registers of mode
w
,wpulse
andr_wpulse
not taking into account non-zero default values of other fields.Decrease
RegisterList.object_hash()
calculation time by 40%. Improves performance ofRegisterCodeGenerator.should_create()
.Improve TOML parsing performance by a factor of ~8 by switching to
rtoml
instead oftomli
package.
Added
Add support for parsing JSON and YAML data files, see here.
Add generation of register records with natively-typed members for each register field to
VhdlRecordPackageGenerator
.Add generation of simulation support package to
VhdlSimulationReadWritePackageGenerator
.Uses VUnit Verification Components for bus operations.
Uses the natively typed records from
VhdlRecordPackageGenerator
for values.Generates the following procedures:
Read/write for each register.
Read/write for each field.
Add generation of simulation support package to
VhdlSimulationWaitUntilPackageGenerator
.Uses VUnit Verification Components for bus operations.
Uses the natively typed records from
VhdlRecordPackageGenerator
for values.Generates the following procedures:
Wait until register equals for each register.
Wait until field equals for each register.
Add generation of a wrapper around axi_lite_reg_file.vhd to
VhdlAxiLiteWrapperGenerator
.Sets correct generics and uses the natively typed records from
VhdlRecordPackageGenerator
for its up/down register values.
Add checks to
Integer.get_value()
andInteger.set_value()
that values are within the configured range of the field.
Breaking changes
Move
RegisterParser
to sub-packagehdl_registers.parser
. Break outfrom_toml()
to separate Python modulehdl_registers.parser.toml
.Rename
module_name
argument ofRegisterParser
andfrom_toml()
toname
.Rename VHDL field conversion function for enumerations from
to_<field name>_slv
toto_slv
.Remove C++ interface header constant
<register array name>_array_length
. Information is instead available as an attributefpga_regs::<module name>::<register array name>::array_length
.Rework code generator API for better performance and scalability.
Remove public members
copy_source_definition
,generated_info
,generated_source_info
fromRegisterList
.Remove
create_vhdl_package
method fromRegisterList
. Movehdl_registers.register_vhdl_generator.RegisterVhdlGenerator
class toVhdlRegisterPackageGenerator
and update API. See VHDL code generator for usage details.Remove
create_c_header
method fromRegisterList
. Movehdl_registers.register_c_generator.RegisterCGenerator
class toCHeaderGenerator
and update API. See C code generator for usage details.Remove
create_cpp_interface
,create_cpp_header
andcreate_cpp_implementation
methods fromRegisterList
. Movehdl_registers.register_cpp_generator.RegisterCppGenerator
class toCppInterfaceGenerator
,CppHeaderGenerator
, andCppImplementationGenerator
, and update API. See C++ code generator for usage details.Remove
create_html_page
,create_html_register_table
andcreate_html_constant_table
methods fromRegisterList
. Movehdl_registers.register_html_generator.RegisterHtmlGenerator
class toHtmlPageGenerator
,HtmlRegisterTableGenerator
, andHtmlConstantTableGenerator
, and update API. See HTML code generator for usage details.Remove
create_python_class
method fromRegisterList
. Movehdl_registers.register_python_generator.RegisterPythonGenerator
class toPythonPickleGenerator
and update API. See Python code generator for usage details.
4.1.0 (2 november 2023)
Changes since previous release
Added
Add support for negative-range integer fields.
4.0.2 (18 october 2023)
Changes since previous release
Fix required Python version in PyPI package.
4.0.1 (11 october 2023)
Changes since previous release
Fix PyPI link to release notes.
4.0.0 (11 october 2023)
Changes since previous release
Fixes
Use
double
data type for generated C/C++ header floating-point constants. Matches the precision in the generated VHDL code.
Breaking changes
Break up
hdl_registers.Constant
class intoBooleanConstant
,FloatConstant
,IntegerConstant
andStringConstant
that are placed in newconstant
sub-package.Move
BitVector
,Bit
andRegisterField
classes andregister_field_type
module from top-level tofield
sub-package.Move
HtmlTranslator
,RegisterCGenerator
,RegisterCodeGenerator
,RegisterCppGenerator
,RegisterHtmlGenerator
,RegisterPythonGenerator
andRegisterVhdlGenerator
classes from top-level togenerator
sub-package.Rename
RegisterField.range
toRegisterField.range_str()
.Remove default value
description=None
for argument toRegisterList.add_constant()
.Remove public method
vhdl_typedef
fromFieldType
class. This logic is instead moved toRegisterVhdlGenerator
.Remove the largely unused “Value (hexadecimal)” constant information column from HTML generator.
Remove textual descriptions of registers/arrays/fields/constants from generated C header.
Added
Add support for unsigned bit vector constants via the
UnsignedVectorConstant
class.Add support for ranged integer register fields via the
Integer
class.Add support for enumeration register fields via the
Enumeration
class.
3.1.0 (25 april 2023)
Changes since previous release
Added
Add support for register constants of type string.
3.0.2 (4 march 2023)
Changes since previous release
Added
Add more comments to generated VHDL.
3.0.1 (3 march 2023)
Changes since previous release
Update project slogan on PyPI to fit within 98 characters.
3.0.0 (3 march 2023)
Changes since previous release
Added
Add field setters and getters to
RegisterCppGenerator
.Add
*_MASK_INVERSE
defines for fields toRegisterCGenerator
.Add support for register constants of boolean and floating point type.
Breaking changes
Remove the field
_mask
and_shift
public constants from the generated C++ interface header. These are not needed now that setters and getters are available.Change to use unresolved VHDL types in
RegisterVhdlGenerator
class.std_ulogic_vector
instead ofstd_logic_vector
.u_signed
instead ofsigned
.u_unsigned
instead ofunsigned
.
Changes
Increase TOML parsing performance by using
tomli
Python package instead oftomlkit
.
2.1.0 (1 april 2022)
Changes since previous release
Added
Add
.RegisterList.create_python_class
method to create a Python pickle file. Read more here.Add optional
field_type
argument toRegisterList.append_register()
andRegister
.Add support for generating
ieee.fixed_pkg
types inRegisterVhdlGenerator
class based on the registerfield_type
.
Fixed
Fix bug where setting default value for bit 31 in a register could fail.
2.0.1 (22 october 2021)
Changes since previous release
Second release to test PyPI deploy. Functionality is identical to tsfpga version 9.0.0.
2.0.0 (22 october 2021)
Initial release to test PyPI deploy. Functionality is identical to tsfpga version 9.0.0.