The hdl-registers project is an open-source HDL register interface code generator fast enough to run in real time. It makes FPGA/ASIC development more fun by automating a lot of time-consuming manual work. It also minimizes the risk of bugs by removing the need for duplicate information. Read more
AXI-Lite register file wrapper using records and native VHDL types for values.
Support packages for compact and efficient simulation.
Complete class with setters and getters for registers and fields.
Includes an abstract interface header for unit test mocking.
C header with register addresses and field information.
HTML website with documentation of registers and fields.
The tool can also be extended by writing your own code generator using a simple but powerful API.
This project is mature and used in many production environments. The maintainers place high focus on quality, with everything having good unit test coverage and a thought-out structure.