Coverage for hdl_registers/generator/vhdl/reserved_keywords.py: 100%
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1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the hdl-registers project, an HDL register generator fast enough to run
5# in real time.
6# https://hdl-registers.com
7# https://github.com/hdl-registers/hdl-registers
8# --------------------------------------------------------------------------------------------------
10# Reserved keywords in the VHDL programming language.
11# Should include everything up until VHDL-2019.
12# From e.g. https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/VHDL-RESERVED-Words
13# Note that they shall all be lowercase here in this set.
14RESERVED_VHDL_KEYWORDS = {
15 "abs",
16 "access",
17 "after",
18 "alias",
19 "all",
20 "and",
21 "architecture",
22 "array",
23 "assert",
24 "attribute",
25 "begin",
26 "block",
27 "body",
28 "buffer",
29 "bus",
30 "case",
31 "component",
32 "configuration",
33 "constant",
34 "disconnect",
35 "downto",
36 "else",
37 "elsif",
38 "end",
39 "entity",
40 "exit",
41 "file",
42 "for",
43 "function",
44 "generate",
45 "generic",
46 "group",
47 "guarded",
48 "if",
49 "impure",
50 "in",
51 "inertial",
52 "inout",
53 "is",
54 "label",
55 "library",
56 "linkage",
57 "literal",
58 "loop",
59 "map",
60 "mod",
61 "nand",
62 "new",
63 "next",
64 "nor",
65 "not",
66 "null",
67 "of",
68 "on",
69 "open",
70 "or",
71 "others",
72 "out",
73 "package",
74 "port",
75 "postponed",
76 "private",
77 "procedure",
78 "process",
79 "pure",
80 "range",
81 "record",
82 "register",
83 "reject",
84 "rem",
85 "report",
86 "return",
87 "rol",
88 "ror",
89 "select",
90 "severity",
91 "shared",
92 "signal",
93 "sla",
94 "sll",
95 "sra",
96 "srl",
97 "subtype",
98 "then",
99 "to",
100 "transport",
101 "type",
102 "unaffected",
103 "units",
104 "until",
105 "use",
106 "variable",
107 "wait",
108 "when",
109 "while",
110 "with",
111 "xnor",
112 "xor",
113}