Coverage for hdl_registers/generator/vhdl/axi_lite/test/test_wrapper.py: 100%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the hdl-registers project, an HDL register generator fast enough to run 

5# in real time. 

6# https://hdl-registers.com 

7# https://github.com/hdl-registers/hdl-registers 

8# -------------------------------------------------------------------------------------------------- 

9 

10""" 

11Some limited unit tests. 

12Note that the generated VHDL code is also simulated in a functional test. 

13""" 

14 

15from hdl_registers.generator.vhdl.axi_lite.wrapper import VhdlAxiLiteWrapperGenerator 

16from hdl_registers.register_list import RegisterList 

17from hdl_registers.register_modes import REGISTER_MODES 

18 

19 

20def test_file_is_not_generated_without_registers(tmp_path): 

21 register_list = RegisterList(name="test", source_definition_file=None) 

22 

23 assert not (VhdlAxiLiteWrapperGenerator(register_list, tmp_path).create()).exists() 

24 

25 register_list.add_constant(name="apa", value=True, description="") 

26 assert not (VhdlAxiLiteWrapperGenerator(register_list, tmp_path).create()).exists() 

27 

28 register_list.append_register(name="hest", mode=REGISTER_MODES["r_w"], description="") 

29 assert (VhdlAxiLiteWrapperGenerator(register_list, tmp_path).create()).exists() 

30 

31 

32def test_re_generating_file_without_registers_should_delete_old_file(tmp_path): 

33 register_list = RegisterList(name="test", source_definition_file=None) 

34 register_list.append_register(name="apa", mode=REGISTER_MODES["r_w"], description="") 

35 

36 assert (VhdlAxiLiteWrapperGenerator(register_list, tmp_path).create()).exists() 

37 

38 register_list.register_objects = [] 

39 assert not (VhdlAxiLiteWrapperGenerator(register_list, tmp_path).create()).exists()