Coverage for hdl_registers/generator/vhdl/test/test_register_package.py: 100%
66 statements
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1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the hdl-registers project, an HDL register generator fast enough to run
5# in real time.
6# https://hdl-registers.com
7# https://github.com/hdl-registers/hdl-registers
8# --------------------------------------------------------------------------------------------------
10"""
11Some limited unit tests that check the generated code.
12Note that the generated VHDL code is also simulated in a functional test.
13"""
15# Third party libraries
16import pytest
17from tsfpga.system_utils import read_file
19# First party libraries
20from hdl_registers import HDL_REGISTERS_TESTS
21from hdl_registers.field.numerical_interpretation import (
22 Signed,
23 SignedFixedPoint,
24 Unsigned,
25 UnsignedFixedPoint,
26)
27from hdl_registers.generator.vhdl.register_package import VhdlRegisterPackageGenerator
28from hdl_registers.parser.toml import from_toml
29from hdl_registers.register_list import RegisterList
30from hdl_registers.register_modes import REGISTER_MODES
33class RegisterConfiguration:
34 def __init__(self, name, source_toml_file):
35 self.register_list = from_toml(name=name, toml_file=source_toml_file)
37 self.register_list.add_constant(name="boolean_constant", value=True, description="")
38 self.register_list.add_constant(name="integer_constant", value=3, description="")
39 self.register_list.add_constant(name="real_constant", value=3.14, description="")
40 self.register_list.add_constant(name="string_constant", value="apa", description="")
42 def test_vhdl_package(self, output_path, test_registers, test_constants):
43 vhdl = read_file(VhdlRegisterPackageGenerator(self.register_list, output_path).create())
45 if test_registers:
46 assert "constant test_reg_map : " in vhdl, vhdl
47 else:
48 assert "constant test_reg_map : " not in vhdl, vhdl
50 if test_constants:
51 assert "constant test_constant_boolean_constant : boolean := true;" in vhdl, vhdl
52 assert "constant test_constant_integer_constant : integer := 3;" in vhdl, vhdl
53 assert "constant test_constant_real_constant : real := 3.14;" in vhdl, vhdl
54 assert 'constant test_constant_string_constant : string := "apa";' in vhdl, vhdl
55 assert (
56 "constant test_constant_base_address_hex : "
57 'unsigned(36 - 1 downto 0) := x"8_0000_0000";' in vhdl
58 ), vhdl
59 assert (
60 "constant test_constant_base_address_bin : "
61 'unsigned(36 - 1 downto 0) := "100000000000000000000000000000000000";' in vhdl
62 ), vhdl
63 else:
64 assert "boolean_constant" not in vhdl, vhdl
65 assert "integer_constant" not in vhdl, vhdl
66 assert "real_constant" not in vhdl, vhdl
67 assert "string_constant" not in vhdl, vhdl
70@pytest.fixture
71def register_configuration():
72 return RegisterConfiguration("test", HDL_REGISTERS_TESTS / "regs_test.toml")
75# False positive for pytest fixtures
76# pylint: disable=redefined-outer-name
79def test_vhdl_package_with_registers_and_constants(tmp_path, register_configuration):
80 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=True)
83def test_vhdl_package_with_registers_and_no_constants(tmp_path, register_configuration):
84 register_configuration.register_list.constants = []
85 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=False)
88def test_vhdl_package_with_constants_and_no_registers(tmp_path, register_configuration):
89 register_configuration.register_list.register_objects = []
90 register_configuration.test_vhdl_package(tmp_path, test_registers=False, test_constants=True)
93def test_vhdl_package_with_only_one_register(tmp_path):
94 """
95 Test that reg_map constant has valid VHDL syntax even when there is only one register.
96 """
97 register_list = RegisterList(name="apa", source_definition_file=None)
98 register_list.append_register(
99 name="hest", mode=REGISTER_MODES["r"], description="a single register"
100 )
101 vhdl = read_file(VhdlRegisterPackageGenerator(register_list, tmp_path).create())
103 expected = """
104 constant apa_reg_map : reg_definition_vec_t(apa_reg_range) := (
105 0 => (idx => apa_hest, reg_type => r)
106 );
108 constant apa_regs_init : apa_regs_t := (
109 0 => "00000000000000000000000000000000"
110 );
111"""
112 assert expected in vhdl, vhdl
115def test_vhdl_typedef(tmp_path):
116 register_list = RegisterList(name="test", source_definition_file=None)
117 register = register_list.append_register("number", REGISTER_MODES["r_w"], "")
119 register.append_bit_vector(
120 name="u0",
121 description="",
122 width=2,
123 default_value="11",
124 numerical_interpretation=Unsigned(bit_width=2),
125 )
127 register.append_bit_vector(
128 name="s0",
129 description="",
130 width=2,
131 default_value="11",
132 numerical_interpretation=Signed(bit_width=2),
133 )
135 register.append_bit_vector(
136 name="ufixed0",
137 description="",
138 width=2,
139 default_value="11",
140 numerical_interpretation=UnsignedFixedPoint(-1, -2),
141 )
142 register.append_bit_vector(
143 name="ufixed1",
144 description="",
145 width=8,
146 default_value="1" * 8,
147 numerical_interpretation=UnsignedFixedPoint(5, -2),
148 )
150 register.append_bit_vector(
151 name="sfixed0",
152 description="",
153 width=2,
154 default_value="11",
155 numerical_interpretation=SignedFixedPoint(-1, -2),
156 )
157 register.append_bit_vector(
158 name="sfixed1",
159 description="",
160 width=6,
161 default_value="1" * 6,
162 numerical_interpretation=SignedFixedPoint(5, 0),
163 )
165 register.append_integer(
166 name="integer0", description="", min_value=1, max_value=3, default_value=2
167 )
169 vhdl = read_file(VhdlRegisterPackageGenerator(register_list, tmp_path).create())
171 assert "subtype test_number_u0_t is u_unsigned(1 downto 0);" in vhdl, vhdl
173 assert "subtype test_number_s0_t is u_signed(1 downto 0);" in vhdl, vhdl
175 assert "subtype test_number_ufixed0_t is ufixed(-1 downto -2);" in vhdl, vhdl
176 assert "subtype test_number_ufixed1_t is ufixed(5 downto -2);" in vhdl, vhdl
178 assert "subtype test_number_sfixed0_t is sfixed(-1 downto -2);" in vhdl, vhdl
179 assert "subtype test_number_sfixed1_t is sfixed(5 downto 0);" in vhdl, vhdl
181 assert "subtype test_number_integer0_t is integer range 1 to 3;" in vhdl, vhdl