Coverage for hdl_registers/generator/vhdl/simulation/test/test_check_package.py: 100%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the hdl-registers project, an HDL register generator fast enough to run 

5# in real time. 

6# https://hdl-registers.com 

7# https://github.com/hdl-registers/hdl-registers 

8# -------------------------------------------------------------------------------------------------- 

9 

10""" 

11Some limited unit tests. 

12Note that the generated VHDL code is also simulated in a functional test. 

13""" 

14 

15from tsfpga.system_utils import read_file 

16 

17from hdl_registers.generator.vhdl.simulation.check_package import ( 

18 VhdlSimulationCheckPackageGenerator, 

19) 

20from hdl_registers.register_list import RegisterList 

21from hdl_registers.register_modes import REGISTER_MODES 

22 

23 

24def test_package_is_not_generated_without_registers(tmp_path): 

25 register_list = RegisterList(name="test", source_definition_file=None) 

26 

27 assert not VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists() 

28 

29 register_list.add_constant(name="apa", value=True, description="") 

30 assert not VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists() 

31 

32 register_list.append_register(name="hest", mode=REGISTER_MODES["r_w"], description="") 

33 assert VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists() 

34 

35 

36def test_re_generating_package_without_registers_should_delete_old_file(tmp_path): 

37 register_list = RegisterList(name="test", source_definition_file=None) 

38 register_list.append_register(name="apa", mode=REGISTER_MODES["r_w"], description="") 

39 

40 assert VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists() 

41 

42 register_list.register_objects = [] 

43 assert not VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists() 

44 

45 

46def test_only_readable_registers_are_included(tmp_path): 

47 register_list = RegisterList(name="test", source_definition_file=None) 

48 

49 register_list.append_register( 

50 name="include_r", mode=REGISTER_MODES["r"], description="" 

51 ).append_bit(name="", description="", default_value="0") 

52 register_list.append_register( 

53 name="exclude_w", mode=REGISTER_MODES["w"], description="" 

54 ).append_bit(name="", description="", default_value="0") 

55 register_list.append_register( 

56 name="include_r_w", mode=REGISTER_MODES["r_w"], description="" 

57 ).append_bit(name="", description="", default_value="0") 

58 register_list.append_register( 

59 name="exclude_wpulse", mode=REGISTER_MODES["wpulse"], description="" 

60 ).append_bit(name="", description="", default_value="0") 

61 register_list.append_register( 

62 name="include_r_wpulse", mode=REGISTER_MODES["r_wpulse"], description="" 

63 ).append_bit(name="", description="", default_value="0") 

64 

65 vhdl = read_file(VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create()) 

66 

67 assert "include_r" in vhdl 

68 assert "include_r_w" in vhdl 

69 assert "include_r_wpulse" in vhdl 

70 assert "exclude" not in vhdl