Coverage for hdl_registers/generator/vhdl/simulation/test/test_check_package.py: 100%
29 statements
« prev ^ index » next coverage.py v7.6.1, created at 2024-09-07 20:51 +0000
« prev ^ index » next coverage.py v7.6.1, created at 2024-09-07 20:51 +0000
1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the hdl-registers project, an HDL register generator fast enough to run
5# in real time.
6# https://hdl-registers.com
7# https://github.com/hdl-registers/hdl-registers
8# --------------------------------------------------------------------------------------------------
10"""
11Some limited unit tests.
12Note that the generated VHDL code is also simulated in a functional test.
13"""
15# Third party libraries
16from tsfpga.system_utils import read_file
18# First party libraries
19from hdl_registers.generator.vhdl.simulation.check_package import (
20 VhdlSimulationCheckPackageGenerator,
21)
22from hdl_registers.register_list import RegisterList
23from hdl_registers.register_modes import REGISTER_MODES
26def test_package_is_not_generated_without_registers(tmp_path):
27 register_list = RegisterList(name="test", source_definition_file=None)
29 assert not VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists()
31 register_list.add_constant(name="apa", value=True, description="")
32 assert not VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists()
34 register_list.append_register(name="hest", mode=REGISTER_MODES["r_w"], description="")
35 assert VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists()
38def test_re_generating_package_without_registers_should_delete_old_file(tmp_path):
39 register_list = RegisterList(name="test", source_definition_file=None)
40 register_list.append_register(name="apa", mode=REGISTER_MODES["r_w"], description="")
42 assert VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists()
44 register_list.register_objects = []
45 assert not VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create().exists()
48def test_only_readable_registers_are_included(tmp_path):
49 register_list = RegisterList(name="test", source_definition_file=None)
51 register_list.append_register(
52 name="include_r", mode=REGISTER_MODES["r"], description=""
53 ).append_bit(name="", description="", default_value="0")
54 register_list.append_register(
55 name="exclude_w", mode=REGISTER_MODES["w"], description=""
56 ).append_bit(name="", description="", default_value="0")
57 register_list.append_register(
58 name="include_r_w", mode=REGISTER_MODES["r_w"], description=""
59 ).append_bit(name="", description="", default_value="0")
60 register_list.append_register(
61 name="exclude_wpulse", mode=REGISTER_MODES["wpulse"], description=""
62 ).append_bit(name="", description="", default_value="0")
63 register_list.append_register(
64 name="include_r_wpulse", mode=REGISTER_MODES["r_wpulse"], description=""
65 ).append_bit(name="", description="", default_value="0")
67 vhdl = read_file(VhdlSimulationCheckPackageGenerator(register_list, tmp_path).create())
69 assert "include_r" in vhdl
70 assert "include_r_w" in vhdl
71 assert "include_r_wpulse" in vhdl
72 assert "exclude" not in vhdl