Coverage for hdl_registers/test/unit/test_register_vhdl_generator.py: 100%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the hdl_registers project, a HDL register generator fast enough to be run 

5# in real time. 

6# https://hdl-registers.com 

7# https://gitlab.com/tsfpga/hdl_registers 

8# -------------------------------------------------------------------------------------------------- 

9 

10""" 

11Some limited unit tests that check the generated code. 

12 

13It is also functionally tested in the file tb_generated_vhdl_package.vhd. 

14That testbench compiles the VHDL package and performs some run-time assertions on the 

15generated values. That test is considered more meaningful and exhaustive than a unit test would be. 

16""" 

17 

18import pytest 

19 

20from tsfpga.system_utils import read_file 

21 

22from hdl_registers import HDL_REGISTERS_TEST 

23from hdl_registers.parser import from_toml 

24from hdl_registers.register_list import RegisterList 

25from hdl_registers.register_field_type import Unsigned, Signed, SignedFixedPoint, UnsignedFixedPoint 

26 

27 

28class RegisterConfiguration: 

29 def __init__(self, module_name, source_toml_file): 

30 self.register_list = from_toml(module_name, source_toml_file) 

31 self.register_list.add_constant("dummy_constant", "3") 

32 self.register_list.add_constant("flappy_constant", "91") 

33 

34 def test_vhdl_package(self, output_path, test_registers, test_constants): 

35 self.register_list.create_vhdl_package(output_path) 

36 vhdl = read_file(output_path / "test_regs_pkg.vhd") 

37 

38 if test_registers: 

39 assert "constant test_reg_map : " in vhdl, vhdl 

40 else: 

41 assert "constant test_reg_map : " not in vhdl, vhdl 

42 

43 if test_constants: 

44 assert "constant test_constant_dummy_constant : integer := 3;" in vhdl, vhdl 

45 else: 

46 assert "constant test_constant_dummy_constant : integer := 3;" not in vhdl, vhdl 

47 

48 

49@pytest.fixture 

50def register_configuration(): 

51 return RegisterConfiguration("test", HDL_REGISTERS_TEST / "regs_test.toml") 

52 

53 

54# False positive for pytest fixtures 

55# pylint: disable=redefined-outer-name 

56 

57 

58def test_vhdl_package_with_registers_and_constants(tmp_path, register_configuration): 

59 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=True) 

60 

61 

62def test_vhdl_package_with_registers_and_no_constants(tmp_path, register_configuration): 

63 register_configuration.register_list.constants = [] 

64 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=False) 

65 

66 

67def test_vhdl_package_with_constants_and_no_registers(tmp_path, register_configuration): 

68 register_configuration.register_list.register_objects = [] 

69 register_configuration.test_vhdl_package(tmp_path, test_registers=False, test_constants=True) 

70 

71 

72def test_vhdl_package_with_only_one_register(tmp_path): 

73 """ 

74 Test that reg_map constant has valid VHDL syntax even when there is only one register. 

75 """ 

76 register_list = RegisterList(name="apa", source_definition_file=None) 

77 register_list.append_register(name="hest", mode="r", description="a single register") 

78 register_list.create_vhdl_package(tmp_path) 

79 vhdl = read_file(tmp_path / "apa_regs_pkg.vhd") 

80 

81 expected = """ 

82 constant apa_reg_map : reg_definition_vec_t(apa_reg_range) := ( 

83 0 => (idx => apa_hest, reg_type => r) 

84 ); 

85 

86 constant apa_regs_init : apa_regs_t := ( 

87 0 => "00000000000000000000000000000000" 

88 ); 

89""" 

90 assert expected in vhdl, vhdl 

91 

92 

93def test_vhdl_typedef(tmp_path): 

94 register_list = RegisterList(name="test", source_definition_file=None) 

95 number = register_list.append_register("number", "r_w", "") 

96 number.append_bit_vector("udata0", "expected unsigned(1 downto 0)", 2, "11", Unsigned()) 

97 number.append_bit_vector("sdata0", "expected signed(1 downto 0)", 2, "11", Signed()) 

98 number.append_bit_vector( 

99 "ufixed0", "expected ufixed(1 downto 0)", 2, "11", UnsignedFixedPoint(-1, -2) 

100 ) 

101 number.append_bit_vector( 

102 "ufixed1", "expected ufixed(5 downto -2)", 8, "1" * 8, UnsignedFixedPoint(5, -2) 

103 ) 

104 number.append_bit_vector( 

105 "ufixed1", "expected ufixed(5 downto -2)", 8, "1" * 8, UnsignedFixedPoint(5, -2) 

106 ) 

107 number.append_bit_vector( 

108 "sfixed0", "expected sfixed(-1 downto -2)", 2, "11", SignedFixedPoint(-1, -2) 

109 ) 

110 number.append_bit_vector( 

111 "sfixed0", "expected sfixed(5 downto 0)", 6, "1" * 6, SignedFixedPoint(5, 0) 

112 ) 

113 

114 register_list.create_vhdl_package(tmp_path) 

115 vhdl = read_file(tmp_path / "test_regs_pkg.vhd") 

116 

117 assert "subtype test_number_udata0_t is unsigned(1 downto 0);" in vhdl, vhdl 

118 assert "subtype test_number_sdata0_t is signed(1 downto 0);" in vhdl, vhdl 

119 assert "subtype test_number_ufixed0_t is ufixed(-1 downto -2);" in vhdl, vhdl 

120 assert "subtype test_number_ufixed1_t is ufixed(5 downto -2);" in vhdl, vhdl 

121 assert "subtype test_number_sfixed0_t is sfixed(-1 downto -2);" in vhdl, vhdl 

122 assert "subtype test_number_sfixed0_t is sfixed(5 downto 0);" in vhdl, vhdl