Coverage for hdl_registers/test/unit/test_register_vhdl_generator.py: 100%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the hdl_registers project, a HDL register generator fast enough to be run 

5# in real time. 

6# https://hdl-registers.com 

7# https://gitlab.com/hdl_registers/hdl_registers 

8# -------------------------------------------------------------------------------------------------- 

9 

10""" 

11Some limited unit tests that check the generated code. 

12 

13It is also functionally tested in the file tb_generated_vhdl_package.vhd. 

14That testbench compiles the VHDL package and performs some run-time assertions on the 

15generated values. That test is considered more meaningful and exhaustive than a unit test would be. 

16""" 

17 

18# Third party libraries 

19import pytest 

20from tsfpga.system_utils import read_file 

21 

22# First party libraries 

23from hdl_registers import HDL_REGISTERS_TEST 

24from hdl_registers.parser import from_toml 

25from hdl_registers.register_field_type import Signed, SignedFixedPoint, Unsigned, UnsignedFixedPoint 

26from hdl_registers.register_list import RegisterList 

27 

28 

29class RegisterConfiguration: 

30 def __init__(self, module_name, source_toml_file): 

31 self.register_list = from_toml(module_name=module_name, toml_file=source_toml_file) 

32 

33 self.register_list.add_constant(name="boolean_constant", value=True) 

34 self.register_list.add_constant(name="integer_constant", value=3) 

35 self.register_list.add_constant(name="real_constant", value=3.14) 

36 

37 def test_vhdl_package(self, output_path, test_registers, test_constants): 

38 self.register_list.create_vhdl_package(output_path) 

39 vhdl = read_file(output_path / "test_regs_pkg.vhd") 

40 

41 if test_registers: 

42 assert "constant test_reg_map : " in vhdl, vhdl 

43 else: 

44 assert "constant test_reg_map : " not in vhdl, vhdl 

45 

46 if test_constants: 

47 assert "constant test_constant_boolean_constant : boolean := true;" in vhdl, vhdl 

48 assert "constant test_constant_integer_constant : integer := 3;" in vhdl, vhdl 

49 assert "constant test_constant_real_constant : real := 3.14;" in vhdl, vhdl 

50 else: 

51 assert "boolean_constant" not in vhdl, vhdl 

52 assert "integer_constant" not in vhdl, vhdl 

53 assert "real_constant" not in vhdl, vhdl 

54 

55 

56@pytest.fixture 

57def register_configuration(): 

58 return RegisterConfiguration("test", HDL_REGISTERS_TEST / "regs_test.toml") 

59 

60 

61# False positive for pytest fixtures 

62# pylint: disable=redefined-outer-name 

63 

64 

65def test_vhdl_package_with_registers_and_constants(tmp_path, register_configuration): 

66 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=True) 

67 

68 

69def test_vhdl_package_with_registers_and_no_constants(tmp_path, register_configuration): 

70 register_configuration.register_list.constants = [] 

71 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=False) 

72 

73 

74def test_vhdl_package_with_constants_and_no_registers(tmp_path, register_configuration): 

75 register_configuration.register_list.register_objects = [] 

76 register_configuration.test_vhdl_package(tmp_path, test_registers=False, test_constants=True) 

77 

78 

79def test_vhdl_package_with_only_one_register(tmp_path): 

80 """ 

81 Test that reg_map constant has valid VHDL syntax even when there is only one register. 

82 """ 

83 register_list = RegisterList(name="apa", source_definition_file=None) 

84 register_list.append_register(name="hest", mode="r", description="a single register") 

85 register_list.create_vhdl_package(tmp_path) 

86 vhdl = read_file(tmp_path / "apa_regs_pkg.vhd") 

87 

88 expected = """ 

89 constant apa_reg_map : reg_definition_vec_t(apa_reg_range) := ( 

90 0 => (idx => apa_hest, reg_type => r) 

91 ); 

92 

93 constant apa_regs_init : apa_regs_t := ( 

94 0 => "00000000000000000000000000000000" 

95 ); 

96""" 

97 assert expected in vhdl, vhdl 

98 

99 

100def test_vhdl_typedef(tmp_path): 

101 register_list = RegisterList(name="test", source_definition_file=None) 

102 number = register_list.append_register("number", "r_w", "") 

103 number.append_bit_vector("udata0", "expected u_unsigned(1 downto 0)", 2, "11", Unsigned()) 

104 number.append_bit_vector("sdata0", "expected u_signed(1 downto 0)", 2, "11", Signed()) 

105 number.append_bit_vector( 

106 "ufixed0", "expected ufixed(1 downto 0)", 2, "11", UnsignedFixedPoint(-1, -2) 

107 ) 

108 number.append_bit_vector( 

109 "ufixed1", "expected ufixed(5 downto -2)", 8, "1" * 8, UnsignedFixedPoint(5, -2) 

110 ) 

111 number.append_bit_vector( 

112 "ufixed1", "expected ufixed(5 downto -2)", 8, "1" * 8, UnsignedFixedPoint(5, -2) 

113 ) 

114 number.append_bit_vector( 

115 "sfixed0", "expected sfixed(-1 downto -2)", 2, "11", SignedFixedPoint(-1, -2) 

116 ) 

117 number.append_bit_vector( 

118 "sfixed0", "expected sfixed(5 downto 0)", 6, "1" * 6, SignedFixedPoint(5, 0) 

119 ) 

120 

121 register_list.create_vhdl_package(tmp_path) 

122 vhdl = read_file(tmp_path / "test_regs_pkg.vhd") 

123 

124 assert "subtype test_number_udata0_t is u_unsigned(1 downto 0);" in vhdl, vhdl 

125 assert "subtype test_number_sdata0_t is u_signed(1 downto 0);" in vhdl, vhdl 

126 assert "subtype test_number_ufixed0_t is ufixed(-1 downto -2);" in vhdl, vhdl 

127 assert "subtype test_number_ufixed1_t is ufixed(5 downto -2);" in vhdl, vhdl 

128 assert "subtype test_number_sfixed0_t is sfixed(-1 downto -2);" in vhdl, vhdl 

129 assert "subtype test_number_sfixed0_t is sfixed(5 downto 0);" in vhdl, vhdl