This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 6.1.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2024-11-20 20:51 at commit 547d42cf1aaa5f86. Register hash 81d8209b61d8521a21cdb30a8c428ed6a2d9db3d.
The following register modes are available.
| Mode | Description |
|---|---|
| Read | Software can read a value that hardware provides. |
| Write | Software can write a value that is available for hardware usage. |
| Read, Write | Software can write a value and read it back. The written value is available for hardware usage. |
| Write-pulse | Software can write a value that is asserted for one clock cycle in hardware. |
| Read, Write-pulse | Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
The following registers make up the register map.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
| config | 0 | 0x0000 | Read, Write | 0x5 | Configuration register. |
| tuser | 3:0 | 0b0101 | Value to set for TUSER in the data stream. | ||
| tid | 11:4 | 0b00000000 | Value to set for TID in the data stream. |
This module does not have any constants.