This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 5.2.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2024-05-09 20:52 at commit 3352559b4412d7fa. Register hash 262328eef2aac3997deca482fc0ecabdbcf3bfa1.
The following register modes are available.
| Mode | Description |
|---|---|
| Read | Bus can read a value that fabric provides. |
| Write | Bus can write a value that is available for fabric usage. |
| Read, Write | Bus can write a value and read it back. The written value is available for fabric usage. |
| Write-pulse | Bus can write a value that is asserted for one clock cycle in fabric. |
| Read, Write-pulse | Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
The following registers make up the register map.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
| config | 0 | 0x0000 | Read, Write | 0x1 | Configuration register. |
| enable | 0 | 0b1 | Enable data passthrough. | ||
| invert | 1 | 0b0 | Optionally enable inversion of data. |
This module does not have any constants.