This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 7.3.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2025-04-01 20:50 at Git commit 228a22928e9a. Register hash 875f95ff1d46cbfb4a58f0314fa90bf2c0b5352a.
The following register modes are available.
| Mode | Description |
|---|---|
Read |
Software can read a value that hardware provides. |
Write |
Software can write a value that is available for hardware usage. |
Read, Write |
Software can write a value and read it back. The written value is available for hardware usage. |
Write-pulse |
Software can write a value that is asserted for one clock cycle in hardware. |
Read, Write-pulse |
Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
The following registers make up the register list.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
conf |
0 |
0x0000 |
Read, Write |
0x1 |
Configuration register. |
enable |
0 |
0b1 |
Enable data passthrough. |
||
invert |
1 |
0b0 |
Optionally enable inversion of data. |
This module does not have any constants.