This document is a specification for the register interface of the FPGA module example.
This file is automatically generated by hdl_registers. Generated 2023-01-29 22:04 from file regs_example.toml at commit 38485d1f4fcdd4f6.
The following register modes are available.
|Read||Bus can read a value that fabric provides.|
|Write||Bus can write a value that is available for fabric usage.|
|Read, Write||Bus can write a value and read it back. The written value is available for fabric usage.|
|Write-pulse||Bus can write a value that is asserted for one clock cycle in fabric.|
|Read, Write-pulse||Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric.|
The following registers make up the register map.
|configuration||0||0x0000||Read, Write||0xB||This is the description of my register.
Rudimentary RST formatting can be used, such as boldface and italics.
|enable||0||0b1||Description of the enable bit field.|
|data_tag||4:1||0b0101||Description of my data_tag bit vector field.|
|idle||0||0b1||'1' when the module is inactive and a new run can be launched.
'0' when the module is working.
|stalling||1||0b0||'1' if the module is currently being stalled.|
|counter||9:2||0b00000000||Number of bursts that have finished.|
|command||2||0x0008||Write-pulse||0x0||The value written to this register will be asserted for one clock cycle in the FPGA fabric.|
|start||0||0b0||Write this bit to start operation.|
|flush||1||0b0||Write this bit to flush data in progress.|
|Register array base_addresses, repeated 3 times. Iterator i ∈ [0, 2].||One set of base addresses for each feature.|
|read_address||3 + i × 2||0x000C + i × 0x0008||Read, Write||0x0|
|address||27:0||0b0000000000000000000000000000||Read address for a 256 MiB address space.|
|write_address||4 + i × 2||0x0010 + i × 0x0008||Read, Write||0x0|
|address||27:0||0b0000000000000000000000000000||Write address for a 256 MiB address space.|
|End register array base_addresses.|
The following constants are part of the register interface.
|axi_data_width||64||0x00000040||Data width of the AXI port used by this module.|
|clock_rate_hz||156250000.0||-||The clock rate used in the system, given in Hertz.|
|supports_pre_filtering||True||-||Will indicate 'True' if the module supports data pre-filtering.|