This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 4.1.1-dev2. Code generator HtmlPageGenerator version 1.0.0. Generated 2023-12-04 10:43 at commit d6ece437d0e3b2bc. Register hash 0374f5fdddb8924a10afac061b0395e46dc08973.
The following register modes are available.
Mode | Description |
---|---|
Read | Bus can read a value that fabric provides. |
Write | Bus can write a value that is available for fabric usage. |
Read, Write | Bus can write a value and read it back. The written value is available for fabric usage. |
Write-pulse | Bus can write a value that is asserted for one clock cycle in fabric. |
Read, Write-pulse | Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
The following registers make up the register map.
Name | Index | Address | Mode | Default value | Description |
---|---|---|---|---|---|
config | 0 | 0x0000 | Read, Write | 0x1 | Configuration register. |
severity_level | 1:0 | warning |
Run-time configuration of severity. Can be set to the following values:
|
||
packet_source | 3:2 | streaming |
Set input mux. Can be set to the following values:
|
This module does not have any constants.