This document is a specification for the register interface of the FPGA module caesar.
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The following register modes are available.
Mode | Description |
---|---|
Read | Software can read a value that hardware provides. |
Write | Software can write a value that is available for hardware usage. |
Read, Write | Software can write a value and read it back. The written value is available for hardware usage. |
Write-pulse | Software can write a value that is asserted for one clock cycle in hardware. |
Read, Write-pulse | Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
The following registers make up the register map.
Name | Index | Address | Mode | Default value | Description |
---|---|---|---|---|---|
config | 0 | 0x0000 | Read, Write | 0x1 | Configuration register. |
severity_level | 1:0 | warning |
Run-time configuration of severity. Can be set to the following values:
|
||
packet_source | 3:2 | streaming |
Set input mux. Can be set to the following values:
|
This module does not have any constants.