This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 4.1.1-dev2. Code generator HtmlPageGenerator version 1.0.0. Generated 2023-12-04 10:43 at commit d6ece437d0e3b2bc. Register hash ab4682176503ca21e3d1e995f4fb0f197c8c3ae8.
The following register modes are available.
| Mode | Description |
|---|---|
| Read | Bus can read a value that fabric provides. |
| Write | Bus can write a value that is available for fabric usage. |
| Read, Write | Bus can write a value and read it back. The written value is available for fabric usage. |
| Write-pulse | Bus can write a value that is asserted for one clock cycle in fabric. |
| Read, Write-pulse | Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
This module does not have any registers.
The following constants are part of the register interface.
| Name | Value | Description |
|---|---|---|
| base_address | 0xA_0000_0000 | Base address for this module on the register bus. |
| data_mask | 0b1100_1111 |