configuration |
0 |
0x0000 |
Read, Write |
0xB |
This is the description of my register.
Rudimentary RST formatting can be used, such as boldface and italics. |
enable |
0 |
|
|
0b1 |
Description of the enable bit field. |
data_tag |
4:1 |
|
|
0b0101 |
Description of my data_tag bit vector field. |
status |
1 |
0x0004 |
Read |
0x1 |
|
idle |
0 |
|
|
0b1 |
'1' when the module is inactive and a new run can be launched.
'0' when the module is working. |
stalling |
1 |
|
|
0b0 |
'1' if the module is currently being stalled. |
counter |
9:2 |
|
|
0b00000000 |
Number of bursts that have finished. |
command |
2 |
0x0008 |
Write-pulse |
0x0 |
The value written to this register will be asserted for one clock cycle in the FPGA fabric. |
start |
0 |
|
|
0b0 |
Write this bit to start operation. |
flush |
1 |
|
|
0b0 |
Write this bit to flush data in progress. |
read_address |
3 + i × 2 |
0x000C + i × 0x0008 |
Read, Write |
0x0 |
|
address |
27:0 |
|
|
0b0000000000000000000000000000 |
Read address for a 256 MiB address space. |
write_address |
4 + i × 2 |
0x0010 + i × 0x0008 |
Read, Write |
0x0 |
|
address |
27:0 |
|
|
0b0000000000000000000000000000 |
Write address for a 256 MiB address space. |