This document is a specification for the register interface of the FPGA module caesar.
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The following register modes are available.
| Mode | Description |
|---|---|
Read |
Software can read a value that hardware provides. |
Write |
Software can write a value that is available for hardware usage. |
Read, Write |
Software can write a value and read it back. The written value is available for hardware usage. |
Write-pulse |
Software can write a value that is asserted for one clock cycle in hardware. |
Read, Write-pulse |
Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
The following registers make up the register list.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
|
Register array base_addresses, repeated 3 times. Iterator i ∈ [0, 2]. |
One set of base addresses for each feature. |
||||
read_address |
0 + i × 2 |
0x0000 + i × 0x0008 |
Read, Write |
0x0 |
|
address |
27:0 |
0b0000000000000000000000000000 |
Read address for a 256 MiB address space. |
||
write_address |
1 + i × 2 |
0x0004 + i × 0x0008 |
Read, Write |
0x0 |
|
address |
27:0 |
0b0000000000000000000000000000 |
Write address for a 256 MiB address space. |
||
|
End register array base_addresses. |
|||||
This module does not have any constants.