This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 4.1.1-dev2. Code generator HtmlPageGenerator version 1.0.0. Generated 2023-12-04 10:43 at commit d6ece437d0e3b2bc. Register hash a0eb931f123c2e423e85d00341e7d7f8047bcffa.
The following register modes are available.
|Read||Bus can read a value that fabric provides.|
|Write||Bus can write a value that is available for fabric usage.|
|Read, Write||Bus can write a value and read it back. The written value is available for fabric usage.|
|Write-pulse||Bus can write a value that is asserted for one clock cycle in fabric.|
|Read, Write-pulse||Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric.|
The following registers make up the register map.
|Register array base_addresses, repeated 3 times. Iterator i ∈ [0, 2].||One set of base addresses for each feature.|
|read_address||0 + i × 2||0x0000 + i × 0x0008||Read, Write||0x0|
|address||27:0||0b0000000000000000000000000000||Read address for a 256 MiB address space.|
|write_address||1 + i × 2||0x0004 + i × 0x0008||Read, Write||0x0|
|address||27:0||0b0000000000000000000000000000||Write address for a 256 MiB address space.|
|End register array base_addresses.|
This module does not have any constants.