Documentation of caesar registers

This document is a specification for the register interface of the FPGA module caesar.

This file is automatically generated by hdl-registers version 6.0.2-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2024-10-03 20:52 at commit 32af2301489cab59. Register hash d398508c05f52d1800bf8d33954a99a6ebc864d8.

Register modes

The following register modes are available.

Mode Description
Read Software can read a value that hardware provides.
Write Software can write a value that is available for hardware usage.
Read, Write Software can write a value and read it back. The written value is available for hardware usage.
Write-pulse Software can write a value that is asserted for one clock cycle in hardware.
Read, Write-pulse Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware.

Registers

The following registers make up the register map.

Name Index Address Mode Default value Description
Register array base_addresses, repeated 3 times. Iterator i ∈ [0, 2]. One set of base addresses for each feature.
read_address 0 + i × 2 0x0000 + i × 0x0008 Read, Write 0x0
  address   27:0 0b0000000000000000000000000000 Read address for a 256 MiB address space.
write_address 1 + i × 2 0x0004 + i × 0x0008 Read, Write 0x0
  address   27:0 0b0000000000000000000000000000 Write address for a 256 MiB address space.

Constants

This module does not have any constants.