This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 5.2.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2024-05-09 20:52 at commit 3352559b4412d7fa. Register hash 5bf25bc5ce7e7bb89d3f05d6ed90c19998888575.
The following register modes are available.
Mode | Description |
---|---|
Read | Bus can read a value that fabric provides. |
Write | Bus can write a value that is available for fabric usage. |
Read, Write | Bus can write a value and read it back. The written value is available for fabric usage. |
Write-pulse | Bus can write a value that is asserted for one clock cycle in fabric. |
Read, Write-pulse | Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
The following registers make up the register map.
Name | Index | Address | Mode | Default value | Description |
---|---|---|---|---|---|
config | 0 | 0x0000 | Read, Write | 0x40 | Configuration register. |
burst_length_bytes | 8:0 | 64 |
The number of bytes to request. Valid numeric range: [1 – 256]. |
||
increment | 11:9 | 0 |
Offset that will be added to data. Valid numeric range: [-4 – 3]. |
||
retry_count | 14:12 | 0 |
Number of retry attempts before giving up. Valid numeric range: [0 – 5]. |
This module does not have any constants.