This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 6.2.1-dev2. Code generator HtmlPageGenerator version 1.0.0. Generated 2024-12-29 20:51 at commit c518991abac6. Register hash 805a50de03b71b95d3523176ad9155b5fe7be903.
The following register modes are available.
| Mode | Description |
|---|---|
| Read | Software can read a value that hardware provides. |
| Write | Software can write a value that is available for hardware usage. |
| Read, Write | Software can write a value and read it back. The written value is available for hardware usage. |
| Write-pulse | Software can write a value that is asserted for one clock cycle in hardware. |
| Read, Write-pulse | Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
The following registers make up the register list.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
| config | 0 | 0x0000 | Read, Write | 0x40 | Configuration register. |
| burst_length_bytes | 8:0 | 64 |
The number of bytes to request. Valid numeric range: [1 – 256]. |
||
| increment | 11:9 | 0 |
Offset that will be added to data. Valid numeric range: [-4 – 3]. |
||
| retry_count | 14:12 | 0 |
Number of retry attempts before giving up. Valid numeric range: [0 – 5]. |
This module does not have any constants.