This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 4.1.1-dev2. Code generator HtmlPageGenerator version 1.0.0. Generated 2023-12-04 10:43 at commit d6ece437d0e3b2bc. Register hash 54f1567c2566683661a466b7eb992f5562934ac8.
The following register modes are available.
| Mode | Description |
|---|---|
| Read | Bus can read a value that fabric provides. |
| Write | Bus can write a value that is available for fabric usage. |
| Read, Write | Bus can write a value and read it back. The written value is available for fabric usage. |
| Write-pulse | Bus can write a value that is asserted for one clock cycle in fabric. |
| Read, Write-pulse | Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
The following registers make up the register map.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
| configuration | 0 | 0x0000 | Read, Write | 0x40 | Configuration register. |
| burst_length_bytes | 8:0 | 64 |
The number of bytes to request. Valid numeric range: [1 – 256]. |
||
| increment | 11:9 | 0 |
Offset that will be added to data. Valid numeric range: [-4 – 3]. |
||
| retry_count | 14:12 | 0 |
Number of retry attempts before giving up. Valid numeric range: [0 – 5]. |
This module does not have any constants.