This document is a specification for the register interface of the FPGA module caesar.
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The following register modes are available.
| Mode | Description |
|---|---|
| Read | Software can read a value that hardware provides. |
| Write | Software can write a value that is available for hardware usage. |
| Read, Write | Software can write a value and read it back. The written value is available for hardware usage. |
| Write-pulse | Software can write a value that is asserted for one clock cycle in hardware. |
| Read, Write-pulse | Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
The following registers make up the register map.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
| interrupt_status | 0 | 0x0000 | Read, Write-pulse | 0x0 | Interrupt status for my module. |
| overflow | 0 | 0b0 | Too high data rate. | ||
| underflow | 1 | 0b0 | Too low data rate. | ||
| interrupt_mask | 1 | 0x0004 | Read, Write | 0x0 | Enable or disable interrupts by setting bitmask. |
| config | 2 | 0x0008 | Read, Write | 0x0 | Generic configuration register. |
This module does not have any constants.