Documentation of caesar registers

This document is a specification for the register interface of the FPGA module caesar.

This file is automatically generated by hdl-registers version 5.1.4-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2024-04-16 20:52 at commit c1d987980d0749fd. Register hash 07ff9f5d363999ae8dc20a7f7f97a7f485a74abb.

Register modes

The following register modes are available.

Mode Description
Read Bus can read a value that fabric provides.
Write Bus can write a value that is available for fabric usage.
Read, Write Bus can write a value and read it back. The written value is available for fabric usage.
Write-pulse Bus can write a value that is asserted for one clock cycle in fabric.
Read, Write-pulse Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric.

Registers

The following registers make up the register map.

Name Index Address Mode Default value Description
interrupt_status 0 0x0000 Read, Write-pulse 0x0 Interrupt status. Clear interrupt(s) by writing the corresponding bitmask.
interrupt_mask 1 0x0004 Read, Write 0x0 Enable or disable interrupts by setting bitmask.
config 2 0x0008 Read, Write 0x0 Generic configuration register.
status 3 0x000C Read 0x0 Generic status register.

Constants

This module does not have any constants.