This document is a specification for the register interface of the FPGA module caesar.
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The following register modes are available.
| Mode | Description |
|---|---|
| Read | Bus can read a value that fabric provides. |
| Write | Bus can write a value that is available for fabric usage. |
| Read, Write | Bus can write a value and read it back. The written value is available for fabric usage. |
| Write-pulse | Bus can write a value that is asserted for one clock cycle in fabric. |
| Read, Write-pulse | Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
The following registers make up the register map.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
| interrupt_status | 0 | 0x0000 | Read, Write-pulse | 0x0 | Interrupt status. Clear interrupt(s) by writing the corresponding bitmask. |
| interrupt_mask | 1 | 0x0004 | Read, Write | 0x0 | Enable or disable interrupts by setting bitmask. |
| config | 2 | 0x0008 | Read, Write | 0x0 | Generic configuration register. |
| status | 3 | 0x000C | Read | 0x0 | Generic status register. |
This module does not have any constants.