This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 8.0.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2025-05-09 20:51 at Git commit f53f19ab11e0. Register hash d07820360d5d22d88d27ca0ad4b90cade97cfc3f.
The following register modes are available.
| Mode | Description |
|---|---|
Read |
Software can read a value that hardware provides. |
Write |
Software can write a value that is available for hardware usage. |
Read, Write |
Software can write a value and read it back. The written value is available for hardware usage. |
Write-pulse |
Software can write a value that is asserted for one clock cycle in hardware. |
Read, Write-pulse |
Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
This module does not have any registers.
The following constants are part of the register interface.
| Name | Value | Description |
|---|---|---|
module_name |
"preprocessing" |
The name of this module, to be used in FPGA as well as software. |
module_description |
"This module removes glitches and filters incoming data." |