Documentation of example registers

This document is a specification for the register interface of the FPGA module example.

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Register modes

The following register modes are available.

Mode Description
Read Bus can read a value that fabric provides.
Write Bus can write a value that is available for fabric usage.
Read, Write Bus can write a value and read it back. The written value is available for fabric usage.
Write-pulse Bus can write a value that is asserted for one clock cycle in fabric.
Read, Write-pulse Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric.

Registers

The following registers make up the register map.

Name Index Address Mode Default value Description
config 0 0x0000 Read, Write 0x3 This is the description of my register.

Rudimentary RST formatting can be used, such as boldface and italics.
  enable   0 0b1 Enable operation.
  direction   2:1 high_z Set the data direction.

Can be set to the following values:
data_in (0):
Receive data from outside the FPGA.
high_z (1):
Set pins to high impedance.

Will not process any incoming data, nor send anything out.
data_out (2):
Send data from FPGA.
status 1 0x0004 Read 0x0
Register array channels, repeated 4 times. Iterator i ∈ [0, 3]. Configuration for each channel.
read_address 2 + i × 2 0x0008 + i × 0x0008 Read, Write 0x0 Read address for DMA data.
config 3 + i × 2 0x000C + i × 0x0008 Write 0x0 Configuration of channel settings.
  enable   0 0b0 Enable this channel.
  tuser   8:1 0b00000000 TUSER value for this channel.
End register array channels.

Constants

The following constants are part of the register interface.

Name Value Description
axi_data_width 64 Data width of the AXI port used by this module.
clock_rate_hz 156250000.0 The clock rate used in the system, given in Hertz.