Documentation of example registers

This document is a specification for the register interface of the FPGA module example.

This file is automatically generated by hdl-registers version 7.3.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2025-04-01 20:50 from file toml_format.toml at Git commit 228a22928e9a. Register hash bb6496bff8f74abb3efe59e498c2b2a3f7b4149a.

Register modes

The following register modes are available.

Mode	Description
Read	Software can read a value that hardware provides.
Write	Software can write a value that is available for hardware usage.
Read, Write	Software can write a value and read it back. The written value is available for hardware usage.
Write-pulse	Software can write a value that is asserted for one clock cycle in hardware.
Read, Write-pulse	Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware.

Registers

The following registers make up the register list.

Name	Index	Address	Mode	Default value	Description
conf	0	0x0000	Read, Write	0x3	This is the description of my register.
enable	0			0b1	Enable operation.
direction	2:1			high_z	Set the data direction. Can be set to the following values: data_in (0): Receive data from outside the FPGA. high_z (1): Set pins to high impedance. Will not process any incoming data, nor send anything out. data_out (2): Send data from FPGA.
status	1	0x0004	Read	0x0
Register array channels, repeated 4 times. Iterator i ∈ [0, 3].					Configuration for each channel.
read_address	2 + i × 2	0x0008 + i × 0x0008	Read, Write	0x0	Read address for DMA data.
conf	3 + i × 2	0x000C + i × 0x0008	Write	0x0	Configuration of channel settings.
enable	0			0b0	Enable this channel.
tuser	8:1			0b00000000	TUSER value for this channel. Below are examples of reStructuredText (RST) formatting which can be used in any description field. It will be rendered in generated HTML documentation. Bold text Italic text Code text Hyperlink Inline math a² + b² = c² Block math: f̃(ω) = (1)/(2π)^∞∫_− ∞f(x)e^− iωx dx
End register array channels.

Constants

The following constants are part of the register interface.

Name	Value	Description
axi_data_width	64	Data width of the AXI port used by this module.
clock_rate_hz	156250000.0	The clock rate used in the system, given in Hertz.