This document is a specification for the register interface of the FPGA module caesar.
This file is automatically generated by hdl-registers version 7.3.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2025-04-01 20:50 at Git commit 228a22928e9a. Register hash 4fc928c3ecfeb4682c3468952959c4763ee5636e.
The following register modes are available.
| Mode | Description |
|---|---|
Read |
Software can read a value that hardware provides. |
Write |
Software can write a value that is available for hardware usage. |
Read, Write |
Software can write a value and read it back. The written value is available for hardware usage. |
Write-pulse |
Software can write a value that is asserted for one clock cycle in hardware. |
Read, Write-pulse |
Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
This module does not have any registers.
The following constants are part of the register interface.
| Name | Value | Description |
|---|---|---|
axi_data_width |
64 |
Data width of the AXI port used by this module. |
burst_length_beats |
256 |