Documentation of caesar registers

This document is a specification for the register interface of the FPGA module caesar.

This file is automatically generated by hdl-registers version 5.2.1-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2024-05-21 20:51 at commit 2f4170d05b13abac. Register hash 4fc928c3ecfeb4682c3468952959c4763ee5636e.

Register modes

The following register modes are available.

Mode Description
Read Bus can read a value that fabric provides.
Write Bus can write a value that is available for fabric usage.
Read, Write Bus can write a value and read it back. The written value is available for fabric usage.
Write-pulse Bus can write a value that is asserted for one clock cycle in fabric.
Read, Write-pulse Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric.

Registers

This module does not have any registers.

Constants

The following constants are part of the register interface.

Name Value Description
axi_data_width 64 Data width of the AXI port used by this module.
burst_length_beats 256