This document is a specification for the register interface of the FPGA module caesar.
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The following register modes are available.
| Mode | Description |
|---|---|
| Read | Bus can read a value that fabric provides. |
| Write | Bus can write a value that is available for fabric usage. |
| Read, Write | Bus can write a value and read it back. The written value is available for fabric usage. |
| Write-pulse | Bus can write a value that is asserted for one clock cycle in fabric. |
| Read, Write-pulse | Bus can read a value that fabric provides. Bus can write a value that is asserted for one clock cycle in fabric. |
This module does not have any registers.
The following constants are part of the register interface.
| Name | Value | Description |
|---|---|---|
| axi_data_width | 64 | Data width of the AXI port used by this module. |
| burst_length_beats | 256 |